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1. 发明申请

US20070134888A1 Back-gated semiconductor device with a storage layer and methods for forming thereof 有权
标题翻译：具有存储层的后门控半导体器件及其形成方法
公开(公告)号：US20070134888A1
公开(公告)日：2007-06-14
申请号：US11300077
申请日：2005-12-14
申请人： Craig Swift , Gowrishankar Chindalore , Thuy Dao , Michael Sadd
发明人： Craig Swift , Gowrishankar Chindalore , Thuy Dao , Michael Sadd
IPC分类号： H01L21/30
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L21/84 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor structure and the layer of the gate material and the storage layer may be located closer to the first side of the second wafer than the semiconductor structure. The method further includes boding the first side of the second wafer to the first wafer. The method further includes removing a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a transistor having a channel region, wherein at least a portion of the channel region is formed from the layer of the semiconductor structure.
摘要翻译：制造半导体器件的方法包括提供第一晶片并提供具有第一侧和第二侧的第二晶片，所述第二晶片包括半导体衬底，存储层和栅极材料层。存储层可以位于半导体结构和栅极材料层之间，并且存储层可以比半导体结构更靠近第二晶片的第一侧。该方法还包括将第二晶片的第一侧布置到第一晶片。该方法还包括去除半导体结构的第一部分以在结合之后留下半导体结构层。该方法还包括形成具有沟道区的晶体管，其中沟道区的至少一部分由半导体结构的层形成。

2. 发明申请

US20070020856A1 Process for forming an electronic device including discontinuous storage elements 失效
标题翻译：用于形成包括不连续存储元件的电子设备的方法
公开(公告)号：US20070020856A1
公开(公告)日：2007-01-25
申请号：US11188935
申请日：2005-07-25
申请人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
发明人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0475 , H01L21/7624 , H01L27/11519 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336
摘要： forming a first gate electrode within the trench after forming the discontinuous storage elements. At least one discontinuous storage element lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and a primary surface of the substrate. The process can also include forming a second gate electrode overlying the first gate electrode and the primary surface of the substrate.
摘要翻译：在形成不连续的存储元件之后，在沟槽内形成第一栅电极。至少一个不连续的存储元件位于第一栅电极的上表面和衬底的主表面之间的海拔处的沟槽的壁处。该工艺还可以包括形成覆盖在第一栅电极和衬底的主表面上的第二栅电极。

3. 发明申请

US20070018222A1 Electronic device including discontinuous storage elements 有权
标题翻译：电子设备包括不连续的存储元件
公开(公告)号：US20070018222A1
公开(公告)日：2007-01-25
申请号：US11188999
申请日：2005-07-25
申请人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
发明人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825
摘要： An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein at least one discontinuous storage element lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and a primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface of the substrate. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.
摘要翻译：电子设备可以包括位于沟槽内的不连续存储元件。在一个实施例中，电子设备可以包括具有包括壁和底部的沟槽的衬底。电子设备还可以包括位于沟槽内的不连续存储元件的一部分。电子器件还可以包括第一栅电极，其中至少一个不连续存储元件沿着沟槽的壁位于第一栅电极的上表面和衬底的主表面之间的高度处。电子器件还可以包括覆盖在第一栅电极和衬底的主表面上的第二栅电极。在另一个实施例中，导线可以电连接到一个或多个存储单元的行或列，而另一个导线可以是更多行或更多列的存储单元。

4. 发明申请

US20070178649A1 Double-gated non-volatile memory and methods for forming thereof 有权
标题翻译：双门非易失性存储器及其形成方法
公开(公告)号：US20070178649A1
公开(公告)日：2007-08-02
申请号：US11341973
申请日：2006-01-27
申请人： Craig Swift , Thuy Dao , Michael Sadd
发明人： Craig Swift , Thuy Dao , Michael Sadd
IPC分类号： H01L21/336 , H01L21/30
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L21/76251 , H01L29/66825 , H01L29/66833 , H01L29/78648 , H01L29/7887 , H01L29/7923
摘要： A method for making a semiconductor device comprises providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor structure, a first storage layer, and a layer of gate material, wherein the first storage layer is located between the semiconductor structure and the layer of gate material and closer to the first side of the second wafer than the semiconductor structure. The method further includes bonding the first side of the second wafer to the first wafer and cleaving away a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a second storage layer over the layer of the semiconductor structure and forming a top gate over the second storage layer.
摘要翻译：制造半导体器件的方法包括提供第一晶片并提供具有第一侧和第二侧的第二晶片，所述第二晶片包括半导体结构，第一存储层和栅极材料层，其中所述第一存储层位于半导体结构和栅极材料层之间并且比半导体结构更靠近第二晶片的第一侧。该方法还包括将第二晶片的第一侧接合到第一晶片并且在结合之后解除半导体结构的第一部分以留下半导体结构层。该方法还包括在半导体结构的层上形成第二存储层，并在第二存储层上形成顶栅。

5. 发明申请

US20070134867A1 Floating gate non-volatile memory and method thereof 有权
标题翻译：浮动门非易失性存储器及其方法
公开(公告)号：US20070134867A1
公开(公告)日：2007-06-14
申请号：US11302937
申请日：2005-12-14
申请人： Michael Sadd , Gowrishankar Chindalore , Cheong Hong
发明人： Michael Sadd , Gowrishankar Chindalore , Cheong Hong
IPC分类号： H01L21/8238
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/4234 , H01L29/7881
摘要： A method is provided which includes forming a first gate overlying a major surface of an electronic device substrate and forming a second gate overlying and spaced apart from the first gate. The method further includes forming a charge storage structure horizontally adjacent to, and continuous along, the first gate and the second gate, wherein a major surface of the charge storage structure is substantially vertical to the major surface of the substrate.
摘要翻译：提供了一种方法，其包括形成覆盖在电子器件基板的主表面上的第一栅极并且形成覆盖并与第一栅极间隔开的第二栅极。该方法还包括形成电荷存储结构，该电荷存储结构沿着第一栅极和第二栅极水平相邻并连续地延伸，其中电荷存储结构的主表面基本上垂直于衬底的主表面。

6. 发明申请

US20060030105A1 Method of discharging a semiconductor device 有权
标题翻译：放电半导体器件的方法
公开(公告)号：US20060030105A1
公开(公告)日：2006-02-09
申请号：US10912825
申请日：2004-08-06
申请人： Erwin Prinz , Ramachandran Muralidhar , Rajesh Rao , Michael Sadd , Robert Steimle , Craig Swift , Bruce White
发明人： Erwin Prinz , Ramachandran Muralidhar , Rajesh Rao , Michael Sadd , Robert Steimle , Craig Swift , Bruce White
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , G11C16/0475 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332
摘要： In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.
摘要翻译：在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电场到纳米团簇放电半导体器件。施加紫外线（UV）光时可能会发生电场。在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。

7. 发明申请

US20070077705A1 Split gate memory cell and method therefor 有权
标题翻译：分闸存储单元及其方法
公开(公告)号：US20070077705A1
公开(公告)日：2007-04-05
申请号：US11240240
申请日：2005-09-30
申请人： Erwin Prinz , Michael Sadd , Robert Steimle
发明人： Erwin Prinz , Michael Sadd , Robert Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/42332
摘要： A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.
摘要翻译：分离栅极存储单元具有选择栅极，控制栅极和电荷存储结构。选择栅极包括位于控制栅极上方的第一部分和不位于控制栅极上方的第二部分。在一个示例中，选择栅极的第一部分具有与控制栅极的侧壁对齐并与电荷存储结构的侧壁对准的侧壁。在一个示例中，控制栅极具有p型导电性。在一个示例中，门可以通过热载流子注入操作来编程，并且可以通过隧道操作来擦除。

8. 发明授权

US06706599B1 Multi-bit non-volatile memory device and method therefor 失效
标题翻译：多位非易失性存储装置及其方法
公开(公告)号：US06706599B1
公开(公告)日：2004-03-16
申请号：US10393065
申请日：2003-03-20
申请人： Michael Sadd , Bruce E. White , Craig T. Swift
发明人： Michael Sadd , Bruce E. White , Craig T. Swift
IPC分类号： H01L218247
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/66825 , H01L29/7887
摘要： A multi-bit non-volatile memory device includes a charge storage layer (14) sandwiched between two insulating layers (12 and 16) formed on a semiconductor substrate (10). A thick oxide layer (18) is formed over the charge storage layer (14) and a minimum feature sized hole is etched in the thick oxide layer (18). An opening is formed in the thick oxide layer (18). Side-wall spacers (60) formed on the inside wall of the hole over the charge storage layer have a void (62) between them that is less than the minimum feature size. The side-wall spacers (60) function to mask portions of the charge storage layer (14), when the charge storage layer is etched away, to form the two separate charge storage regions (55 and 57) under the side-wall spacers (60). The device can be manufactured using only one mask step. Separating the charge storage regions prevents lateral conduction of charge in the nitride.
摘要翻译：多位非易失性存储器件包括夹在形成在半导体衬底（10）上的两个绝缘层（12和16）之间的电荷存储层（14）。在电荷存储层（14）之上形成厚的氧化物层（18），并且在厚氧化物层（18）中蚀刻最小特征尺寸的孔。在厚氧化物层（18）中形成开口。形成在电荷存储层上的孔的内壁上的侧壁间隔物（60）在它们之间具有小于最小特征尺寸的空隙（62）。当电荷存储层被蚀刻掉时，侧壁间隔物（60）用于掩蔽电荷存储层（14）的部分，以形成侧壁间隔物下面的两个分开的电荷存储区域（55和57） 60）。该装置可以仅使用一个掩模步骤制造。分离电荷存储区域可防止氮化物中电荷的横向传导。

9. 发明申请

US20110024821A1 PUSH-PULL FPGA CELL 审中-公开
标题翻译：推拉FPGA单元
公开(公告)号：US20110024821A1
公开(公告)日：2011-02-03
申请号：US12903493
申请日：2010-10-13
申请人： Zhigang Wang , Fethi Dhaoui , Michael Sadd , John McCollum , Frank Hawley
发明人： Zhigang Wang , Fethi Dhaoui , Michael Sadd , John McCollum , Frank Hawley
IPC分类号： H01L29/68
CPC分类号： G11C16/0441
摘要： A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.
摘要翻译：闪存单元包括具有源极，漏极，浮置栅极和控制栅极的p沟道闪存晶体管，具有源极的n沟道闪存晶体管，耦合到p沟道闪存晶体管的漏极的漏极，浮动栅极和控制栅极，具有耦合到p沟道闪存晶体管和n沟道闪存晶体管的漏极的栅极的开关晶体管，源极和漏极以及n沟道辅助晶体管，其具有漏极，其耦合到p沟道闪存晶体管和n沟道闪存晶体管的漏极，耦合到固定电位的源极和栅极。

10. 发明申请

US20100149873A1 PUSH-PULL FPGA CELL 有权
标题翻译：推拉FPGA单元
公开(公告)号：US20100149873A1
公开(公告)日：2010-06-17
申请号：US12334059
申请日：2008-12-12
申请人： Zhigang Wang , Fethi Dhaoui , Michael Sadd , John McCollum , Frank Hawley
发明人： Zhigang Wang , Fethi Dhaoui , Michael Sadd , John McCollum , Frank Hawley
IPC分类号： G11C16/04 , G11C5/06
CPC分类号： G11C16/0441
摘要： A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.
摘要翻译：闪存单元包括具有源极，漏极，浮置栅极和控制栅极的p沟道闪存晶体管，具有源极的n沟道闪存晶体管，耦合到p沟道闪存晶体管的漏极的漏极，浮动栅极和控制栅极，具有耦合到p沟道闪存晶体管和n沟道闪存晶体管的漏极的栅极的开关晶体管，源极和漏极以及n沟道辅助晶体管，其具有漏极，其耦合到p沟道闪存晶体管和n沟道闪存晶体管的漏极，耦合到固定电位的源极和栅极。

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