专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070018222A1 Electronic device including discontinuous storage elements 有权
标题翻译：电子设备包括不连续的存储元件
公开(公告)号：US20070018222A1
公开(公告)日：2007-01-25
申请号：US11188999
申请日：2005-07-25
申请人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
发明人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825
摘要： An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein at least one discontinuous storage element lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and a primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface of the substrate. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.
摘要翻译：电子设备可以包括位于沟槽内的不连续存储元件。在一个实施例中，电子设备可以包括具有包括壁和底部的沟槽的衬底。电子设备还可以包括位于沟槽内的不连续存储元件的一部分。电子器件还可以包括第一栅电极，其中至少一个不连续存储元件沿着沟槽的壁位于第一栅电极的上表面和衬底的主表面之间的高度处。电子器件还可以包括覆盖在第一栅电极和衬底的主表面上的第二栅电极。在另一个实施例中，导线可以电连接到一个或多个存储单元的行或列，而另一个导线可以是更多行或更多列的存储单元。

2. 发明申请

US20070020856A1 Process for forming an electronic device including discontinuous storage elements 失效
标题翻译：用于形成包括不连续存储元件的电子设备的方法
公开(公告)号：US20070020856A1
公开(公告)日：2007-01-25
申请号：US11188935
申请日：2005-07-25
申请人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
发明人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0475 , H01L21/7624 , H01L27/11519 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336
摘要： forming a first gate electrode within the trench after forming the discontinuous storage elements. At least one discontinuous storage element lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and a primary surface of the substrate. The process can also include forming a second gate electrode overlying the first gate electrode and the primary surface of the substrate.
摘要翻译：在形成不连续的存储元件之后，在沟槽内形成第一栅电极。至少一个不连续的存储元件位于第一栅电极的上表面和衬底的主表面之间的海拔处的沟槽的壁处。该工艺还可以包括形成覆盖在第一栅电极和衬底的主表面上的第二栅电极。

3. 发明授权

US5605855A Process for fabricating a graded-channel MOS device 失效
标题翻译：用于制造渐变通道MOS器件的工艺
公开(公告)号：US5605855A
公开(公告)日：1997-02-25
申请号：US395339
申请日：1995-02-28
申请人： Ko-Min Chang , Marius Orlowski , Craig Swift , Shih-Wei Sun , Shiang-Chyong Luo
发明人： Ko-Min Chang , Marius Orlowski , Craig Swift , Shih-Wei Sun , Shiang-Chyong Luo
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L29/10 , H01L21/8234
CPC分类号： H01L29/66583 , H01L21/2652 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/66553
摘要： A process for fabricating a graded-channel MOS device includes the formation of a masking layer (16) on the surface of a semiconductor substrate (10) and separated from the surface by a gate oxide layer (12). A first doped region (22) is formed in a channel region (20) of the semiconductor substrate (10) using the masking layer (16) as a doping mask. A second doped region (24) is formed in the channel region (20) and extends from the principal surface (14) of the semiconductor substrate (10) to the first doped region (22). A gate electrode (34) is formed within an opening (18) in the masking layer (16) and aligned to the channel region (20). Upon removal of the masking layer (16) source and drain regions (36, 38) are formed in the semiconductor substrate (10) and aligned to the gate electrode (34).
摘要翻译：用于制造渐变沟道MOS器件的工艺包括在半导体衬底（10）的表面上形成掩模层（16），并通过栅氧化层（12）从表面分离。使用掩模层（16）作为掺杂掩模，在半导体衬底（10）的沟道区（20）中形成第一掺杂区（22）。第二掺杂区域（24）形成在沟道区域（20）中并且从半导体衬底（10）的主表面（14）延伸到第一掺杂区域（22）。栅极电极（34）形成在掩模层（16）的开口（18）内，并与沟道区域（20）对准。在去除掩模层（16）时，源极和漏极区（36,38）形成在半导体衬底（10）中并与栅电极（34）对齐。

4. 发明申请

US20070218669A1 Method of forming a semiconductor device and structure thereof 失效
标题翻译：形成半导体器件的方法及其结构
公开(公告)号：US20070218669A1
公开(公告)日：2007-09-20
申请号：US11376412
申请日：2006-03-15
申请人： Chi Nan Li , Ko-Min Chang , Cheong Hong
发明人： Chi Nan Li , Ko-Min Chang , Cheong Hong
IPC分类号： H01L21/4763
CPC分类号： H01L29/7923 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7887
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate comprising silicon, forming a layer of dielectric on the surface of the semiconductor substrate, forming a gate electrode comprising silicon over the layer of dielectric, recessing the layer of dielectric under the gate electrode, filling the recess with a discrete charge storage material, oxidizing a portion of the gate electrode, and oxidizing a portion of the semiconductor substrate.
摘要翻译：一种形成半导体器件的方法包括提供包括硅的半导体衬底，在半导体衬底的表面上形成电介质层，在电介质层上形成包含硅的栅电极，使栅电极下的电介质层凹陷，用分散的电荷存储材料填充凹槽，氧化栅电极的一部分，以及氧化半导体衬底的一部分。

5. 发明授权

US08921155B2 Resistive random access memory (RAM) cell and method for forming 有权
标题翻译：电阻随机存取存储器（RAM）单元及其形成方法
公开(公告)号：US08921155B2
公开(公告)日：2014-12-30
申请号：US13085217
申请日：2011-04-12
申请人： Feng Zhou , Ko-Min Chang , Cheong Min Hong
发明人： Feng Zhou , Ko-Min Chang , Cheong Min Hong
IPC分类号： H01L21/027 , H01L45/00
CPC分类号： H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675
摘要： A resistive random access memory cell uses a substrate and includes a gate stack over the substrate. The gate stack includes a first copper layer over the substrate, a copper oxide layer over the first copper layer, and a second copper layer over the copper oxide layer.
摘要翻译：电阻式随机存取存储器单元使用衬底并且在衬底上包括栅极堆叠。栅极堆叠包括在衬底上的第一铜层，在第一铜层上方的氧化铜层和氧化铜层上的第二铜层。

6. 发明授权

US06791883B2 Program and erase in a thin film storage non-volatile memory 有权
标题翻译：在薄膜存储非易失性存储器中编程和擦除
公开(公告)号：US06791883B2
公开(公告)日：2004-09-14
申请号：US10178658
申请日：2002-06-24
申请人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
发明人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
IPC分类号： G11C1600
CPC分类号： G11C16/0466
摘要： A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.
摘要翻译：具有薄膜电介质存储元件的非易失性存储器通过热载流子注入（HCI）编程并通过隧道擦除。这种存储器的存储单元的典型结构是硅，氧化物，氮化物，氧化物和硅（SONOS）。热载波注入为SONOS提供相对快速的编程，而隧道提供擦除，避免了通常伴随热载流子注入进行编程的热孔擦除（HHE）类型擦除的困难。 HHE对电介质的破坏性更大，导致可靠性问题。 HHE还具有相对较窄的擦除区域，可能不完全匹配HCI编程的模式，从而导致不完整的擦除。隧道擦除有效地覆盖整个区域，所以不用担心不完全擦除。虽然隧道擦除比HHE慢，但擦除时间在系统操作中通常不如编程时间那么重要。

7. 发明授权

US5646060A Method for making an EEPROM cell with isolation transistor 失效
标题翻译：用隔离晶体管制造EEPROM单元的方法
公开(公告)号：US5646060A
公开(公告)日：1997-07-08
申请号：US471619
申请日：1995-05-30
申请人： Ko-Min Chang , Danny Pak-Chum Shum , Kuo-Tung Chang
发明人： Ko-Min Chang , Danny Pak-Chum Shum , Kuo-Tung Chang
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L29/7883
摘要： An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source region (52) of the floating gate transistor. The isolation transistor is not biased during a program operation of the cell, enabling a thin tunnel dielectric (less than 120 angstroms) to be used beneath all portions of both gates within the cell. Thus, the need for both a conventional tunnel dielectric and a gate dielectric is eliminated. The cell tolerates over-erasure, can be programmed at low programming voltages, and has good current drive due to the thin tunnel dielectric throughout the cell.
摘要翻译： EEPROM单元（40）包括浮栅晶体管（47）和隔离晶体管（45）。浮动栅极（48）和隔离栅极（46）均形成在电池内的隧道电介质（44）上。隔离栅极耦合到浮栅晶体管的掺杂源极区（52）。在单元的编程操作期间，隔离晶体管不被偏置，使得能够在单元内的两个栅极的所有部分下方使用薄的隧道电介质（小于120埃）。因此，消除了对常规隧道电介质和栅极电介质的需要。电池容忍过度擦除，可以在低编程电压下编程，并且由于整个电池中的薄隧道电介质而具有良好的电流驱动。

8. 发明授权

US5258949A Nonvolatile memory with enhanced carrier generation and method for programming the same 失效
标题翻译：具有增强载波生成的非易失性存储器和用于编程的方法
公开(公告)号：US5258949A
公开(公告)日：1993-11-02
申请号：US620813
申请日：1990-12-03
申请人： Ko-Min Chang , Ming-Bing Chang
发明人： Ko-Min Chang , Ming-Bing Chang
IPC分类号： G11C17/00 , G11C16/04 , G11C16/12 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C16/12 , H01L29/7885
摘要： Programming speed of a nonvolatile memory is improved by enhancing carrier generation. In one form, a nonvolatile memory has a control gate which overlies a channel region in a substrate. A floating gate overlies a portion of the channel region and is positioned between the substrate and the control gate. A source and a drain are formed in the substrate, being displaced by the channel region. A first programming voltage is applied to the drain to create an electric field at a junction between the drain and channel region. Current is forced into the source and through the substrate in order to enhance carrier generation at the junction between the drain and channel region, thereby increasing an electric field at the junction. A second programming voltage, having a ramp shaped leading edge, is applied to the control gate to increase the electrical field and to program the memory to a predetermined logic state.
摘要翻译：通过增强载体生成来提高非易失性存储器的编程速度。在一种形式中，非易失性存储器具有覆盖在衬底中的沟道区域的控制栅极。浮动栅极覆盖沟道区的一部分并位于衬底和控制栅之间。源极和漏极形成在衬底中，被沟道区域置换。将第一编程电压施加到漏极，以在漏极和沟道区域之间的结处产生电场。电流被迫进入源极并通过衬底，以便增强在漏极和沟道区域之间的结处的载流子产生，从而增加了结处的电场。具有斜坡形状的前沿的第二编程电压被施加到控制栅极以增加电场并将存储器编程到预定的逻辑状态。

9. 发明授权

US5130769A Nonvolatile memory cell 失效
标题翻译：非易失性存储单元
公开(公告)号：US5130769A
公开(公告)日：1992-07-14
申请号：US700837
申请日：1991-05-16
申请人： Clinton C. K. Kuo , Ko-Min Chang
发明人： Clinton C. K. Kuo , Ko-Min Chang
IPC分类号： G11C17/00 , H01L21/8247 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42368 , H01L29/7885
摘要： A floating gate is utilized which has two portions. A first portion overlies the channel region formed between the source and drain. The control gate overlies this portion of the floating gate and the remaining portion of the channel region forming an enhancement transistor. The second portion of the floating gate extends from the first portion over a thin oxide tunnel area of the source. An additional diode implant forming a junction with the drain region is provided to regulate the current flow through the drain, particularly during erasure.
摘要翻译：使用一个浮动栅极，它有两个部分。第一部分覆盖形成在源极和漏极之间的沟道区域。控制栅极覆盖浮置栅极的该部分，并且沟道区域的剩余部分形成增强晶体管。浮动栅极的第二部分从源极的薄氧化物隧道区域上的第一部分延伸。提供形成与漏极区的结的另外的二极管注入，以调节通过漏极的电流，特别是在擦除期间。

10. 发明申请

US20150349142A1 SPLIT GATE MEMORY CELL WITH IMPROVED ERASE PERFORMANCE 有权
标题翻译：具有改进的擦除性能的分离器门存储器单元
公开(公告)号：US20150349142A1
公开(公告)日：2015-12-03
申请号：US14288975
申请日：2014-05-28
申请人： BRIAN A. WINSTEAD , Ko-Min Chang , Craig T. Swift
发明人： BRIAN A. WINSTEAD , Ko-Min Chang , Craig T. Swift
IPC分类号： H01L29/792 , H01L29/51 , H01L21/28 , G11C16/14
CPC分类号： H01L21/28282 , G11C16/0425 , H01L21/28273 , H01L29/42328 , H01L29/42332 , H01L29/7881
摘要： A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer.
摘要翻译：半导体器件包括半导体衬底，在衬底的一部分上的电荷存储堆叠。电荷存储堆叠包括第一电介质层，与第一介电层接触的纳米晶体层，与纳米晶体层接触并与其接触的第二电介质层，在第二介电层上并与第二介电层接触的氮化物层，以及在氮化物层上的第三电介质层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式