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1. 发明申请

WO2011155705A2 COMPOSITION FOR INHIBITING HYPERLIPIDEMIA AND OBESITY BY INHIBITING INTESTINAL ABSORPTION OF CHOLESTEROL 审中-公开
标题翻译：通过抑制胆固醇的吸收来抑制高脂血症和肥胖的组合物
公开(公告)号：WO2011155705A2
公开(公告)日：2011-12-15
申请号：PCT/KR2011003007
申请日：2011-04-25
申请人： ADBIOTECH CO LTD , BIOCELTRAN CO LTD , JANG SANG HO , CHOI SOO YOUNG , LEE YEOM PYO , AN JAE JIN , CHEONG HONG GUL , KWON HYUCK SE , PARK JEONG KEUM , BAEK DOO YEON
发明人： JANG SANG HO , CHOI SOO YOUNG , LEE YEOM PYO , AN JAE JIN , CHEONG HONG GUL , KWON HYUCK SE , PARK JEONG KEUM , BAEK DOO YEON
IPC分类号： A61K39/395 , A61P3/00 , A61P3/04
CPC分类号： C07K16/18 , C07K2317/11 , C07K2317/23 , C07K2317/76
摘要： The present invention relates to a composition for inhibiting hyperlipidemia and obesity by inhibiting intestinal absorption of cholesterol. An egg yolk-derived IgY-type antibody against Niemann-Pick C1-Like1 (NPC1L1) is contained, as an active ingredient, in the composition of the present invention and adhered to Niemann-Pick C1-Like1 (NPC1L1) in intestines, wherein the NPC1L1 serves as a cholesterol transport protein in intestines, so as to disrupt binding between cholesterol and the cholesterol transport protein, thereby basically blocking in vivo absorption of cholesterol and thus preventing hyperlipidemia and obesity.
摘要翻译：本发明涉及通过抑制胆固醇的肠吸收来抑制高脂血症和肥胖的组合物。在本发明的组合物中含有蛋黄来源的抗Niemann-Pick C1-Like1（NPC1L1）的IgY型抗体作为活性成分，并粘附到肠中的Niemann-Pick C1-Like1（NPC1L1），其中 NPC1L1在肠中作为胆固醇转运蛋白，从而破坏胆固醇和胆固醇转运蛋白之间的结合，从而基本上阻止胆固醇的体内吸收，从而防止高脂血症和肥胖。

2. 发明申请

WO2011155705A3 COMPOSITION FOR INHIBITING HYPERLIPIDEMIA AND OBESITY BY INHIBITING INTESTINAL ABSORPTION OF CHOLESTEROL 审中-公开
标题翻译：通过抑制胆固醇的吸收来抑制高脂血症和肥胖的组合物
公开(公告)号：WO2011155705A3
公开(公告)日：2012-04-19
申请号：PCT/KR2011003007
申请日：2011-04-25
申请人： ADBIOTECH CO LTD , BIOCELTRAN CO LTD , JANG SANG HO , CHOI SOO YOUNG , LEE YEOM PYO , AN JAE JIN , CHEONG HONG GUL , KWON HYUCK SE , PARK JEONG KEUM , BAEK DOO YEON
发明人： JANG SANG HO , CHOI SOO YOUNG , LEE YEOM PYO , AN JAE JIN , CHEONG HONG GUL , KWON HYUCK SE , PARK JEONG KEUM , BAEK DOO YEON
IPC分类号： A61K39/395 , A61P3/00 , A61P3/04
CPC分类号： C07K16/18 , C07K2317/11 , C07K2317/23 , C07K2317/76
摘要： The present invention relates to a composition for inhibiting hyperlipidemia and obesity by inhibiting intestinal absorption of cholesterol. An egg yolk-derived IgY-type antibody against Niemann-Pick C1-Like1 (NPC1L1) is contained, as an active ingredient, in the composition of the present invention and adhered to Niemann-Pick C1-Like1 (NPC1L1) in intestines, wherein the NPC1L1 serves as a cholesterol transport protein in intestines, so as to disrupt binding between cholesterol and the cholesterol transport protein, thereby basically blocking in vivo absorption of cholesterol and thus preventing hyperlipidemia and obesity.
摘要翻译：本发明涉及通过抑制胆固醇的肠吸收来抑制高脂血症和肥胖的组合物。在本发明的组合物中含有蛋黄来源的抗Niemann-Pick C1-Like1（NPC1L1）的IgY型抗体作为活性成分，并粘附到肠中的Niemann-Pick C1-Like1（NPC1L1），其中 NPC1L1在肠中作为胆固醇转运蛋白，从而破坏胆固醇和胆固醇转运蛋白之间的结合，从而基本上阻止胆固醇的体内吸收，从而防止高脂血症和肥胖。

3. 发明申请

US20070134867A1 Floating gate non-volatile memory and method thereof 有权
标题翻译：浮动门非易失性存储器及其方法
公开(公告)号：US20070134867A1
公开(公告)日：2007-06-14
申请号：US11302937
申请日：2005-12-14
申请人： Michael Sadd , Gowrishankar Chindalore , Cheong Hong
发明人： Michael Sadd , Gowrishankar Chindalore , Cheong Hong
IPC分类号： H01L21/8238
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/4234 , H01L29/7881
摘要： A method is provided which includes forming a first gate overlying a major surface of an electronic device substrate and forming a second gate overlying and spaced apart from the first gate. The method further includes forming a charge storage structure horizontally adjacent to, and continuous along, the first gate and the second gate, wherein a major surface of the charge storage structure is substantially vertical to the major surface of the substrate.
摘要翻译：提供了一种方法，其包括形成覆盖在电子器件基板的主表面上的第一栅极并且形成覆盖并与第一栅极间隔开的第二栅极。该方法还包括形成电荷存储结构，该电荷存储结构沿着第一栅极和第二栅极水平相邻并连续地延伸，其中电荷存储结构的主表面基本上垂直于衬底的主表面。

4. 发明申请

US20070019472A1 Electronic device including a memory array and conductive lines 有权
标题翻译：电子设备包括存储器阵列和导线
公开(公告)号：US20070019472A1
公开(公告)日：2007-01-25
申请号：US11188898
申请日：2005-07-25
申请人： Jane Yater , Gowrishankar Chindalore , Cheong Hong
发明人： Jane Yater , Gowrishankar Chindalore , Cheong Hong
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.
摘要翻译：电子电路可以包括第一存储单元和第二存储单元。在一个实施例中，第一和第二存储器单元的源极/漏极区域可彼此电连接。源极/漏极区域可以电浮动，而不管载流子流过存储器单元的沟道区域的方向如何。在另一个实施例中，与第一存储器单元相比，第一存储单元可以电连接到第一栅极线，并且第二存储单元可以电连接到更多数量的栅极线。在另一方面，第一和第二存储器单元连接到相同的位线。当编程或读取第一存储器单元或第二存储单元或其任何组合时，这种位线可以电浮动。

5. 发明申请

US20070018232A1 Nonvolatile storage array with continuous control gate employing hot carrier injection programming 有权
标题翻译：具有采用热载流子注入编程的连续控制栅极的非易失存储阵列
公开(公告)号：US20070018232A1
公开(公告)日：2007-01-25
申请号：US11188582
申请日：2005-07-25
申请人： Gowrishankar Chindalore , Cheong Hong , Craig Swift
发明人： Gowrishankar Chindalore , Cheong Hong , Craig Swift
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L29/4232 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7923
摘要： An array of storage cells include a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.
摘要翻译：存储单元阵列包括限定在半导体衬底中的第一沟槽下面的第一源极/漏极区域和衬底中的第二沟槽下面的第二源极/漏极区域。电荷存储堆叠线路中的每个沟槽，其中电荷存储堆叠包括不连续存储元件（DSE）层。控制门覆盖在第一沟槽上。控制栅极可以垂直于沟槽延伸并穿过第一和第二沟槽。在另一实现中，控制栅极与沟槽平行地延伸。存储单元可以包括占据第一和第二沟槽之间的衬底的上表面的一个或多个扩散区域。扩散区域可以驻留在平行于沟槽的第一和第二控制栅极之间。或者，一对扩散区域可以发生在垂直于沟槽的控制栅极的任一侧上。

6. 发明授权

US07112490B1 Hot carrier injection programmable structure including discontinuous storage elements and spacer control gates in a trench 有权
标题翻译：热载体注入可编程结构，包括沟槽中的不连续存储元件和间隔物控制栅极
公开(公告)号：US07112490B1
公开(公告)日：2006-09-26
申请号：US11188604
申请日：2005-07-25
申请人： Cheong Hong , Chi-Nan Li
发明人： Cheong Hong , Chi-Nan Li
IPC分类号： H01L21/336 , H01L21/84 , H01L21/8242 , H01L29/76 , G11C11/34
CPC分类号： G11C16/10 , B82Y10/00 , H01L27/115 , H01L27/11556 , H01L29/4232 , H01L29/42332 , H01L29/42336 , H01L29/7881 , H01L29/792
摘要： A programmable storage device includes a first diffusion region underlying a portion of a first trench defined in a semiconductor substrate and a second diffusion region occupying an upper portion of the substrate adjacent to the first trench. The device includes a charge storage stack lining sidewalls and a portion of a floor of the first trench. The charge storage stack includes a layer of discontinuous storage elements (DSEs). Electrically conductive spacers formed on opposing sidewalls of the first trench adjacent to respective charge storage stacks serve as control gates for the device. The DSEs may be silicon, polysilicon, metal, silicon nitride, or metal nitride nanocrystals or nanoclusters. The storage stack includes a top dielectric of CVD silicon oxide overlying the nanocrystals overlying a bottom dielectric of thermally formed silicon dioxide. The device includes first and second injection regions in the layer of DSEs proximal to the first and second diffusion regions.
摘要翻译：可编程存储装置包括在半导体衬底中限定的第一沟槽的部分下面的第一扩散区域和占据与第一沟槽相邻的衬底的上部的第二扩散区域。该装置包括一个电荷存储层，衬垫侧壁和第一沟槽的一部分地板。电荷存储堆叠包括不连续存储元件（DSE）层。形成在与相应电荷存储堆叠相邻的第一沟槽的相对侧壁上的导电间隔件用作该装置的控制栅极。 DSE可以是硅，多晶硅，金属，氮化硅或金属氮化物纳米晶体或纳米团簇。存储堆叠包括覆盖在热形成的二氧化硅的底部电介质上的纳米晶体上的CVD氧化硅的顶部电介质。该装置包括位于第一和第二扩散区域附近的DSE层中的第一和第二注入区域。

7. 发明申请

US20070054452A1 SOURCE SIDE INJECTION STORAGE DEVICE WITH SPACER GATES AND METHOD THEREFOR 有权
标题翻译：来源侧注射装置与间隔闸门及其方法
公开(公告)号：US20070054452A1
公开(公告)日：2007-03-08
申请号：US11536190
申请日：2006-09-28
申请人： Cheong Hong , Gowrishankar Chindalore
发明人： Cheong Hong , Gowrishankar Chindalore
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7923
摘要： A storage device structure (10) has two bits of storage per control gate (34) and uses source side injection (SSI) to provide lower programming current. A control gate (34) overlies a drain electrode formed by a doped region (22) that is positioned in a semiconductor substrate (12). Two select gates (49 and 50) are implemented with conductive sidewall spacers adjacent to and lateral to the control gate (34). A source doped region (60) is positioned in the semiconductor substrate (12) adjacent to one of the select gates for providing a source of electrons to be injected into a storage layer (42) underlying the control gate. Lower programming results from the SSI method of programming and a compact memory cell size exists.
摘要翻译：存储装置结构（10）每个控制栅极（34）具有两位存储，并且使用源极侧注入（SSI）来提供较低的编程电流。控制栅极（34）覆盖由位于半导体衬底（12）中的掺杂区域（22）形成的漏电极。两个选择栅极（49和50）被实现为与控制栅极（34）相邻并在其侧面的导电侧壁间隔件。源极掺杂区域（60）位于与选择栅极之一相邻的半导体衬底（12）中，用于提供要注入到控制栅极下面的存储层（42）中的电子源。存在来自编程的SSI方法的较低编程结果和紧凑的存储单元尺寸。

8. 发明申请

US20070020856A1 Process for forming an electronic device including discontinuous storage elements 失效
标题翻译：用于形成包括不连续存储元件的电子设备的方法
公开(公告)号：US20070020856A1
公开(公告)日：2007-01-25
申请号：US11188935
申请日：2005-07-25
申请人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
发明人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0475 , H01L21/7624 , H01L27/11519 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336
摘要： forming a first gate electrode within the trench after forming the discontinuous storage elements. At least one discontinuous storage element lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and a primary surface of the substrate. The process can also include forming a second gate electrode overlying the first gate electrode and the primary surface of the substrate.
摘要翻译：在形成不连续的存储元件之后，在沟槽内形成第一栅电极。至少一个不连续的存储元件位于第一栅电极的上表面和衬底的主表面之间的海拔处的沟槽的壁处。该工艺还可以包括形成覆盖在第一栅电极和衬底的主表面上的第二栅电极。

9. 发明申请

US20080019178A1 ELECTRONIC DEVICE INCLUDING A MEMORY ARRAY AND CONDUCTIVE LINES 有权
标题翻译：包括记忆阵列和导电线的电子设备
公开(公告)号：US20080019178A1
公开(公告)日：2008-01-24
申请号：US11834391
申请日：2007-08-06
申请人： Jane Yater , Gowrishankar Chindalore , Cheong Hong
发明人： Jane Yater , Gowrishankar Chindalore , Cheong Hong
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/10
摘要： An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.
摘要翻译：电子电路可以包括第一存储单元和第二存储单元。在一个实施例中，第一和第二存储器单元的源极/漏极区域可彼此电连接。源极/漏极区域可以电浮动，而不管载流子流过存储器单元的沟道区域的方向如何。在另一个实施例中，与第一存储器单元相比，第一存储单元可以电连接到第一栅极线，并且第二存储单元可以电连接到更多数量的栅极线。在另一方面，第一和第二存储器单元连接到相同的位线。当编程或读取第一存储器单元或第二存储单元或其任何组合时，这种位线可以电浮动。

10. 发明申请

US20070020831A1 Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming 有权
标题翻译：使用热载流子注入编程的连续控制栅极制造非易失性存储阵列的方法
公开(公告)号：US20070020831A1
公开(公告)日：2007-01-25
申请号：US11188583
申请日：2005-07-25
申请人： Gowrishankar Chindalore , Cheong Hong , Craig Swift
发明人： Gowrishankar Chindalore , Cheong Hong , Craig Swift
IPC分类号： H01L21/8234
CPC分类号： H01L29/7887 , B82Y10/00 , H01L27/115 , H01L27/11519 , H01L27/11556 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/42348 , H01L29/42352 , H01L29/7923 , H01L29/7926
摘要： A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.
摘要翻译：制造存储单元阵列的方法包括在半导体衬底中限定的第一沟槽下面的第一源极/漏极区域和在衬底中的第二沟槽下面的第二源极/漏极区域。电荷存储堆叠线路中的每个沟槽，其中电荷存储堆叠包括不连续存储元件（DSE）层。控制门覆盖在第一沟槽上。控制栅极可以垂直于沟槽延伸并穿过第一和第二沟槽。在另一实现中，控制栅极与沟槽平行地延伸。存储单元可以包括占据第一和第二沟槽之间的衬底的上表面的一个或多个扩散区域。扩散区域可以驻留在平行于沟槽的第一和第二控制栅极之间。或者，一对扩散区域可以发生在垂直于沟槽的控制栅极的任一侧上。

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