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1. 发明申请

US20060030105A1 Method of discharging a semiconductor device 有权
标题翻译：放电半导体器件的方法
公开(公告)号：US20060030105A1
公开(公告)日：2006-02-09
申请号：US10912825
申请日：2004-08-06
申请人： Erwin Prinz , Ramachandran Muralidhar , Rajesh Rao , Michael Sadd , Robert Steimle , Craig Swift , Bruce White
发明人： Erwin Prinz , Ramachandran Muralidhar , Rajesh Rao , Michael Sadd , Robert Steimle , Craig Swift , Bruce White
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , G11C16/0475 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332
摘要： In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.
摘要翻译：在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电场到纳米团簇放电半导体器件。施加紫外线（UV）光时可能会发生电场。在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。

2. 发明申请

US20050059213A1 Semiconductor device with nanoclusters 有权
公开(公告)号：US20050059213A1
公开(公告)日：2005-03-17
申请号：US10663621
申请日：2003-09-16
申请人： Robert Steimle , Ramachandran Muralidhar , Wayne Paulson , Rajesh Rao , Bruce White , Erwin Prinz
发明人： Robert Steimle , Ramachandran Muralidhar , Wayne Paulson , Rajesh Rao , Bruce White , Erwin Prinz
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/115 , H01L29/423
CPC分类号： B82Y10/00 , H01L21/28273 , H01L27/115 , H01L29/42332
摘要： A process of forming a device with nanoclusters. The process includes forming nanoclusters (e.g. silicon nanocrystals) and forming an oxidation barrier layer over the nanoclusters to inhibit oxidizing agents from oxidizing the nanoclusters during a subsequent formation of a dielectric of the device. At least a portion of the oxidation barrier layer is removed after the formation of the dielectric. In one example, the device is a memory wherein the nanoclusters are utilized as charge storage locations for charge storage transistors of the memory. In this example, the oxidation barrier layer protects the nanoclusters from oxidizing agents due to the formation of gate dielectric for high voltage transistors of the memory.

3. 发明申请

US20060211199A1 Method of removing nanoclusters in a semiconductor device 有权
标题翻译：在半导体器件中去除纳米团簇的方法
公开(公告)号：US20060211199A1
公开(公告)日：2006-09-21
申请号：US11082094
申请日：2005-03-16
申请人： Rajesh Rao , Ramachandran Muralidhar , Robert Steimle
发明人： Rajesh Rao , Ramachandran Muralidhar , Robert Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/30604 , H01L21/3065 , H01L29/42332 , H01L29/66825
摘要： A method for removing nanoclusters from a semiconductor device includes etching a selected portion of an insulating layer, flowing a reducing gas over the semiconductor device at a temperature in a range of 400-900 degrees Celsius, and flowing a gas comprising halogen over the semiconductor device a temperature in a range of 400-900 degrees Celsius. In another form, a method for removing the nanoclusters includes implanting germanium or nitrogen into the nanoclusters, etching a selected portion of the insulating layer using a dry etch process, and removing the layer of nanoclusters using a wet etch process that is selective to an insulating layer.
摘要翻译：一种用于从半导体器件中去除纳米团簇的方法包括：在400-900摄氏度的温度范围内蚀刻绝缘层的选定部分，使还原气体在半导体器件上流动，并使包含卤素的气体流过半导体器件温度在400-900摄氏度的范围内。在另一种形式中，用于去除纳米团簇的方法包括将锗或氮注入到纳米团簇中，使用干蚀刻工艺蚀刻绝缘层的选定部分，以及使用对绝缘选择性的湿蚀刻工艺去除纳米团簇层层。

4. 发明申请

US20060194438A1 METHOD OF FORMING A NANOCLUSTER CHARGE STORAGE DEVICE 有权
标题翻译：形成纳米碳管充电储存装置的方法
公开(公告)号：US20060194438A1
公开(公告)日：2006-08-31
申请号：US10876820
申请日：2004-06-25
申请人： Rajesh Rao , Ramachandran Muralidhar , Robert Steimle , Gowrishankar Chindalore
发明人： Rajesh Rao , Ramachandran Muralidhar , Robert Steimle , Gowrishankar Chindalore
IPC分类号： H01L21/302 , H01L31/112 , H01L21/36
CPC分类号： H01L27/11546 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L27/11573 , H01L29/42332
摘要： A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters. Gate electrodes of devices peripheral to the memory cell devices also use the second-formed polysilicon-containing layer.
摘要翻译：通过使用覆盖纳米团簇的中间双重多晶氮化物控制电极堆叠形成多个存储单元器件。堆叠包括第一形成的多晶氮化物层和第二形成的含多晶硅的层。第二形成的含多晶硅的层从包含多个存储单元的区域中去除。在一种形式中，第二形成的含多晶硅的层还包含也被去除的氮化物部分，从而留下用于存储单元器件的第一形成的多晶氮化物层。在另一种形式中，第二形成的含硅层不含有氮化物，并且还去除了第一形成的多晶氮化物层的氮化物部分。在后一种形式中，在剩余的多晶硅层上形成随后的氮化物层。在这两种形式中，器件的顶部部分被保护免受氧化，从而保持下面的纳米簇的尺寸和质量。存储单元器件外围的器件的栅电极也使用第二形成的含多晶硅的层。

5. 发明申请

US20050191808A1 Method for removing nanoclusters from selected regions 失效
标题翻译：从选定区域去除纳米团簇的方法
公开(公告)号：US20050191808A1
公开(公告)日：2005-09-01
申请号：US10787510
申请日：2004-02-26
申请人： Robert Steimle , Jane Yater , Gowrishankar Chindalore , Craig Swift , Steven Anderson , Ramachandran Muralidhar
发明人： Robert Steimle , Jane Yater , Gowrishankar Chindalore , Craig Swift , Steven Anderson , Ramachandran Muralidhar
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/336 , H01L21/44 , H01L21/8247 , H01L27/105 , H01L29/792
CPC分类号： H01L21/32135 , B82Y10/00 , H01L21/28273 , H01L21/32134 , H01L27/105 , H01L27/11521 , H01L27/11526
摘要： Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.
摘要翻译：纳米簇被覆盖在集成电路上，然后从不需要纳米团簇的区域去除。在毛毯沉积之前在纳米团簇不需要的那些区域中形成牺牲层。然后去除纳米团簇和牺牲层。在一种形式中，牺牲层包括沉积的含氮化物或含氧化物层。或者，牺牲层包括先前用于在衬底中形成隔离区域的衬垫氧化物或衬垫氮化物层中的至少一个。然后可以将纳米簇装置和非纳群集装置集成到相同的集成电路上。牺牲层的使用保护下层，从而防止随后形成的非纳群集装置的性能下降。

6. 发明申请

US20060166452A1 Non-volatile nanocrystal memory and method therefor 有权
标题翻译：非挥发性纳米晶体记忆及其方法
公开(公告)号：US20060166452A1
公开(公告)日：2006-07-27
申请号：US11043826
申请日：2005-01-26
申请人： Rajesh Rao , Ramachandran Muralidhar , Bruce White
发明人： Rajesh Rao , Ramachandran Muralidhar , Bruce White
IPC分类号： H01L21/331
CPC分类号： H01L29/42348 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/518
摘要： A nanocrystal non-volatile memory (NVM) has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals where the concentration of electron/hole traps tend to be the highest and is reduced toward the control gate where the concentration of electron/hole traps is lower. This has been found to have the beneficial effect of reducing the number of locations where charge can be trapped.
摘要翻译：纳米晶体非易失性存储器（NVM）在控制栅极和纳米晶体之间具有电介质，其具有足够的氮含量以减少电介质中的电子被俘获的位置。这是通过对氮浓度进行分级而实现的。靠近纳米晶体的氮浓度最高，其中电子/空穴阱的浓度趋于最高，并且朝向电子/空穴陷阱的浓度较低的对照栅极减小。已经发现这具有减少电荷被捕获的位置数量的有益效果。

7. 发明申请

US20060105522A1 Method of forming a nanocluster charge storage device 有权
标题翻译：形成纳米团簇电荷存储装置的方法
公开(公告)号：US20060105522A1
公开(公告)日：2006-05-18
申请号：US10987047
申请日：2004-11-12
申请人： Robert Steimle , Ramachandran Muralidhar , Bruce White
发明人： Robert Steimle , Ramachandran Muralidhar , Bruce White
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/823462 , H01L27/11526 , H01L27/11546 , H01L27/11573
摘要： An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.
摘要翻译：集成电路和形成具有存储器部分的集成电路的方法使存储器部分中的纳米簇存储元件的氧化量最小化。集成电路的第一区域具有非存储器件，每个都具有由单个导电材料层形成的控制电极或栅极。集成电路的第二区域具有多个存储单元，每个存储单元具有至少两个彼此重叠的导电材料层的控制电极。当操作并且形成单个栅电极时，至少两个导电层处于基本相同的电势。在一种形式中，每个存储单元栅极具有覆盖在纳米团簇存储层上的两个多晶硅层。

8. 发明申请

US20080105945A1 METHOD OF FORMING A NANOCLUSTER CHARGE STORAGE DEVICE 有权
标题翻译：形成纳米碳管充电储存装置的方法
公开(公告)号：US20080105945A1
公开(公告)日：2008-05-08
申请号：US11964309
申请日：2007-12-26
申请人： Robert Steimle , Ramachandran Muralidhar , Bruce White
发明人： Robert Steimle , Ramachandran Muralidhar , Bruce White
IPC分类号： H01L27/07
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/823462 , H01L27/11526 , H01L27/11546 , H01L27/11573
摘要： An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.
摘要翻译：集成电路和形成具有存储器部分的集成电路的方法使存储器部分中的纳米簇存储元件的氧化量最小化。集成电路的第一区域具有非存储器件，每个都具有由单个导电材料层形成的控制电极或栅极。集成电路的第二区域具有多个存储单元，每个存储单元具有至少两个彼此重叠的导电材料层的控制电极。当操作并且形成单个栅电极时，至少两个导电层处于基本相同的电势。在一种形式中，每个存储单元栅极具有覆盖在纳米团簇存储层上的两个多晶硅层。

9. 发明申请

US20070004146A1 Semiconductor fabrication process for integrating formation of embedded nonvolatile storage device with formation of multiple transistor device types 有权
标题翻译：用于集成嵌入式非易失性存储装置的形成与形成多晶体管器件类型的半导体制造工艺
公开(公告)号：US20070004146A1
公开(公告)日：2007-01-04
申请号：US11172728
申请日：2005-07-01
申请人： Erwin Prinz , Ramachandran Muralidhar
发明人： Erwin Prinz , Ramachandran Muralidhar
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/823857 , Y10S438/962
摘要： A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.
摘要翻译：半导体制造工艺包括在覆盖衬底的第一区域的隧道氧化物上形成多晶硅纳米晶体。沉积第二电介质覆盖在第一区域和第二区域上。在不提供覆盖第一区域中的第二电介质的任何保护层的情况下，进行额外的热氧化步骤而不氧化纳米晶体。然后将栅极电极膜沉积在第二电介质上并被图案化以形成第一和第二栅电极。第二电介质可以是退火的CVD氧化物。额外的热氧化可以包括通过干式氧化形成覆盖在半导体衬底的第三区域上的第三电介质。干燥氧化在第二区域中产生第二电介质下面的界面氧化硅。然后可以暴露基板的第四区域的上表面，并在第四区域的上表面上形成第四电介质。

10. 发明申请

US20050057964A1 MEMORY WITH CHARGE STORAGE LOCATIONS AND ADJACENT GATE STRUCTURES 有权
标题翻译：具有充电储存位置和相似门结构的存储器
公开(公告)号：US20050057964A1
公开(公告)日：2005-03-17
申请号：US10443908
申请日：2003-05-22
申请人： Leo Mathew , Robert Steimle , Ramachandran Muralidhar
发明人： Leo Mathew , Robert Steimle , Ramachandran Muralidhar
IPC分类号： G11C11/34 , G11C16/04 , H01L21/28 , H01L21/336 , H01L29/788 , H01L29/792
CPC分类号： B82Y10/00 , G11C16/0458 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L29/66818 , H01L29/66825 , H01L29/785 , H01L29/7855 , H01L29/7887 , H01L29/7923
摘要： A memory having gate structures adjacent opposing sidewalls of a semiconductor structure including a channel region and a plurality of charge storage locations between the gate structures and the opposing sidewalls. The channel region is located between two current terminal regions, which in one example serve as the source/drain regions. A memory cell can be implemented in an array of memory cells wherein one gate structure is coupled to one word line and the other gate structure is coupled to another word line. In one example, each cell includes four charge storage locations, each for storing one bit of data.
摘要翻译：一种存储器，其具有邻近半导体结构的相对侧壁的栅极结构，该半导体结构包括沟道区和栅极结构与相对侧壁之间的多个电荷存储位置。沟道区域位于两个电流端子区域之间，在一个示例中，该区域用作源极/漏极区域。存储器单元可以在存储单元的阵列中实现，其中一个栅极结构耦合到一个字线，而另一个栅极结构耦合到另一个字线。在一个示例中，每个单元包括四个电荷存储位置，每个用于存储一位数据。

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