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1. 发明授权

US06855979B2 Multi-bit non-volatile memory device and method therefor 失效
标题翻译：多位非易失性存储器件及其方法
公开(公告)号：US06855979B2
公开(公告)日：2005-02-15
申请号：US10769228
申请日：2004-01-30
申请人： Michael Sadd , Bruce E. White , Craig T. Swift
发明人： Michael Sadd , Bruce E. White , Craig T. Swift
IPC分类号： H01L21/28 , H01L21/336 , H01L29/788 , H01L29/76
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/66825 , H01L29/7887
摘要： A multi-bit non-volatile memory device includes a charge storage layer (14) sandwiched between two insulating layers (12 and 16) formed on a semiconductor substrate (10). A thick oxide layer (18) is formed over the charge storage layer (14) and a minimum feature sized hole is etched in the thick oxide layer (18). An opening is formed in the thick oxide layer (18). Side-wall spacers (60) formed on the inside wall of the hole over the charge storage layer have a void (62) between them that is less than the minimum feature size. The side-wall spacers (60) function to mask portions of the charge storage layer (14), when the charge storage layer is etched away, to form the two separate charge storage regions (55 and 57) under the side-wall spacers (60). The device can be manufactured using only one mask step. Separating the charge storage regions prevents lateral conduction of charge in the nitride.
摘要翻译：多位非易失性存储器件包括夹在形成在半导体衬底（10）上的两个绝缘层（12和16）之间的电荷存储层（14）。在电荷存储层（14）之上形成厚的氧化物层（18），并且在厚氧化物层（18）中蚀刻最小特征尺寸的孔。在厚氧化物层（18）中形成开口。形成在电荷存储层上的孔的内壁上的侧壁间隔物（60）在它们之间具有小于最小特征尺寸的空隙（62）。当电荷存储层被蚀刻掉时，侧壁间隔物（60）用于掩蔽电荷存储层（14）的部分，以形成侧壁间隔物下面的两个分开的电荷存储区域（55和57） 60）。该装置可以仅使用一个掩模步骤制造。分离电荷存储区域可防止氮化物中电荷的横向传导。

2. 发明授权

US06706599B1 Multi-bit non-volatile memory device and method therefor 失效
标题翻译：多位非易失性存储装置及其方法
公开(公告)号：US06706599B1
公开(公告)日：2004-03-16
申请号：US10393065
申请日：2003-03-20
申请人： Michael Sadd , Bruce E. White , Craig T. Swift
发明人： Michael Sadd , Bruce E. White , Craig T. Swift
IPC分类号： H01L218247
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/66825 , H01L29/7887
摘要： A multi-bit non-volatile memory device includes a charge storage layer (14) sandwiched between two insulating layers (12 and 16) formed on a semiconductor substrate (10). A thick oxide layer (18) is formed over the charge storage layer (14) and a minimum feature sized hole is etched in the thick oxide layer (18). An opening is formed in the thick oxide layer (18). Side-wall spacers (60) formed on the inside wall of the hole over the charge storage layer have a void (62) between them that is less than the minimum feature size. The side-wall spacers (60) function to mask portions of the charge storage layer (14), when the charge storage layer is etched away, to form the two separate charge storage regions (55 and 57) under the side-wall spacers (60). The device can be manufactured using only one mask step. Separating the charge storage regions prevents lateral conduction of charge in the nitride.
摘要翻译：多位非易失性存储器件包括夹在形成在半导体衬底（10）上的两个绝缘层（12和16）之间的电荷存储层（14）。在电荷存储层（14）之上形成厚的氧化物层（18），并且在厚氧化物层（18）中蚀刻最小特征尺寸的孔。在厚氧化物层（18）中形成开口。形成在电荷存储层上的孔的内壁上的侧壁间隔物（60）在它们之间具有小于最小特征尺寸的空隙（62）。当电荷存储层被蚀刻掉时，侧壁间隔物（60）用于掩蔽电荷存储层（14）的部分，以形成侧壁间隔物下面的两个分开的电荷存储区域（55和57） 60）。该装置可以仅使用一个掩模步骤制造。分离电荷存储区域可防止氮化物中电荷的横向传导。

3. 发明授权

US07160775B2 Method of discharging a semiconductor device 有权
标题翻译：放电半导体器件的方法
公开(公告)号：US07160775B2
公开(公告)日：2007-01-09
申请号：US10912825
申请日：2004-08-06
申请人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
发明人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , G11C16/0475 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332
摘要： In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.
摘要翻译：在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电场到纳米团簇放电半导体器件。施加紫外线（UV）光时可能会发生电场。在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。

4. 发明申请

US20080121966A1 Nanocrystal non-volatile memory cell and method therefor 有权
标题翻译：纳米晶体非挥发性记忆体及其方法
公开(公告)号：US20080121966A1
公开(公告)日：2008-05-29
申请号：US11530053
申请日：2006-09-08
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

5. 发明授权

US06297095B1 Memory device that includes passivated nanoclusters and method for manufacture 有权
标题翻译：包含钝化纳米簇的记忆体装置及其制造方法
公开(公告)号：US06297095B1
公开(公告)日：2001-10-02
申请号：US09596399
申请日：2000-06-16
申请人： Ramachandran Muralidhar , Chitra K. Subramanian , Sucharita Madhukar , Bruce E. White , Michael A. Sadd , Sufi Zafar , David L. O'Meara , Bich-Yen Nguyen
发明人： Ramachandran Muralidhar , Chitra K. Subramanian , Sucharita Madhukar , Bruce E. White , Michael A. Sadd , Sufi Zafar , David L. O'Meara , Bich-Yen Nguyen
IPC分类号： H01L21336
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/66439 , H01L29/7888
摘要： A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are then formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).
摘要翻译：提出了一种具有浮动栅极的半导体存储器件，其包括多个纳米团簇（21）和用于制造这种器件的技术。该器件通过首先提供其上形成有隧道介电层（14）的半导体衬底（12）形成。然后在隧道介电层（14）上生长多个纳米团簇（19）。在纳米团簇（21）生长之后，在纳米团簇（21）上形成控制电介质层（20）。为了防止形成的纳米团簇（21）的氧化，可以在形成控制电介质层（20）之前使用各种技术将纳米团簇（21）进行封装。然后在控制电介质（20）上形成栅极（24），并且选择性地去除不在栅电极下面的控制电介质，多个纳米团簇和栅极电介质的部分。在形成间隔物（35）之后，然后通过注入在半导体层（12）中形成源极和漏极区域（32,34），使得沟道区域形成在栅极下面的源极和漏极区域（32,34）之间电极（24）。

6. 发明授权

US08373221B2 Nanocluster charge storage device 有权
标题翻译：纳米簇电荷存储装置
公开(公告)号：US08373221B2
公开(公告)日：2013-02-12
申请号：US11964309
申请日：2007-12-26
申请人： Robert F. Steimle , Ramachandran Muralidhar , Bruce E. White
发明人： Robert F. Steimle , Ramachandran Muralidhar , Bruce E. White
IPC分类号： H01L29/792
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/823462 , H01L27/11526 , H01L27/11546 , H01L27/11573
摘要： An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.
摘要翻译：集成电路和形成具有存储器部分的集成电路的方法使存储器部分中的纳米簇存储元件的氧化量最小化。集成电路的第一区域具有非存储器件，每个都具有由单个导电材料层形成的控制电极或栅极。集成电路的第二区域具有多个存储单元，每个存储单元具有至少两个彼此重叠的导电材料层的控制电极。当操作并且形成单个栅电极时，至少两个导电层处于基本相同的电势。在一种形式中，每个存储单元栅极具有覆盖在纳米团簇存储层上的两个多晶硅层。

7. 发明申请

US20090166712A1 NANOCRYSTAL NON-VOLATILE MEMORY CELL AND METHOD THEREFOR 有权
标题翻译： NANOCRYSTAL非易失性记忆细胞及其方法
公开(公告)号：US20090166712A1
公开(公告)日：2009-07-02
申请号：US12397849
申请日：2009-03-04
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L29/78
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

8. 发明申请

US20080164512A1 LIGHT ERASABLE MEMORY AND METHOD THEREFOR 有权
标题翻译：光可擦除存储器及其方法
公开(公告)号：US20080164512A1
公开(公告)日：2008-07-10
申请号：US11620075
申请日：2007-01-05
申请人： Rajesh A. Rao , Leo Mathew , Ramachandran Muralidhar , Bruce E. White
发明人： Rajesh A. Rao , Leo Mathew , Ramachandran Muralidhar , Bruce E. White
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L21/84 , H01L27/112 , H01L27/11206 , H01L27/11517 , H01L27/1203 , H01L27/15 , H01L29/66825 , H01L29/788
摘要： A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.
摘要翻译：半导体器件具有半导体衬底，其又具有顶部半导体层部分和顶部半导体层部分下方的主要支撑部分。互连层在半导体层之上。存储器阵列位于顶部半导体层部分和互连层的一部分中。通过去除主要支撑部分的至少一部分并且在移除步骤之后，从与互连层相对的一侧将光施加到存储器阵列来擦除存储器。结果是存储器阵列从背面接收光并被擦除。

9. 发明授权

US07820491B2 Light erasable memory and method therefor 有权
标题翻译：光可擦除记忆及其方法
公开(公告)号：US07820491B2
公开(公告)日：2010-10-26
申请号：US11620075
申请日：2007-01-05
申请人： Rajesh A. Rao , Leo Mathew , Ramachandran Muralidhar , Bruce E. White
发明人： Rajesh A. Rao , Leo Mathew , Ramachandran Muralidhar , Bruce E. White
IPC分类号： H01L21/82 , G11C16/04
CPC分类号： H01L27/105 , H01L21/84 , H01L27/112 , H01L27/11206 , H01L27/11517 , H01L27/1203 , H01L27/15 , H01L29/66825 , H01L29/788
摘要： A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.
摘要翻译：半导体器件具有半导体衬底，其又具有顶部半导体层部分和顶部半导体层部分下方的主要支撑部分。互连层在半导体层之上。存储器阵列位于顶部半导体层部分和互连层的一部分中。通过去除主要支撑部分的至少一部分并且在移除步骤之后，从与互连层相对的一侧将光施加到存储器阵列来擦除存储器。结果是存储器阵列从背面接收光并被擦除。

10. 发明申请

US20090294919A1 METHOD OF FORMING A FINFET AND STRUCTURE 有权
标题翻译：形成FINFET和结构的方法
公开(公告)号：US20090294919A1
公开(公告)日：2009-12-03
申请号：US12130158
申请日：2008-05-30
申请人： Tab A. Stephens , Leo Mathew , Lakshmanna Vishnubholta , Bruce E. White
发明人： Tab A. Stephens , Leo Mathew , Lakshmanna Vishnubholta , Bruce E. White
IPC分类号： H01L23/58 , H01L21/311
CPC分类号： H01L21/02057 , H01L29/66795 , H01L29/66818
摘要： A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX layer, leaving an exposed portion of the BOX layer. The method further includes exposing a top surface of the exposed portion of the BOX layer to an oxide etch resistant species to form a thin oxide etch resistant layer overlying the exposed portion of the BOX layer.
摘要翻译：提供一种用于处理至少包括掩埋氧化物（BOX）层和半导体材料层的衬底的方法。该方法包括蚀刻半导体材料层以形成覆盖BOX层的垂直半导体材料结构，留下BOX层的暴露部分。该方法还包括将BOX层的暴露部分的顶表面暴露于抗氧化物蚀刻物质以形成覆盖BOX层的暴露部分的薄氧化物耐蚀刻层。

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