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1. 发明授权

US09419095B2 Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process 有权
标题翻译：最后一个进程中的伪栅极的制造方法和栅极最后工艺中的虚拟栅极的制造方法
公开(公告)号：US09419095B2
公开(公告)日：2016-08-16
申请号：US14119864
申请日：2012-12-12
申请人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
发明人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
IPC分类号： H01L21/338 , H01L29/66 , H01L29/423 , H01L29/51 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28123 , H01L29/42364 , H01L29/513 , H01L29/518
摘要： A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.
摘要翻译：提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成光致抗蚀剂线，并修整所形成的光致抗蚀剂线，使得修整的光致抗蚀剂线的宽度小于或等于22nm; 并根据修整的光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层无定形硅。

2. 发明申请

US20120252225A1 SEMICONDUCTOR FABRICATION METHOD 审中-公开
标题翻译：半导体制造方法
公开(公告)号：US20120252225A1
公开(公告)日：2012-10-04
申请号：US13140549
申请日：2011-04-11
申请人： Chunlong Li , Junfeng Li
发明人： Chunlong Li , Junfeng Li
IPC分类号： H01L21/316 , B82Y40/00
CPC分类号： H01L21/02238
摘要： A semiconductor fabrication method is provided, in which a protective layer is deposited on the dummy wafer such that the protective layer fully encases the dummy wafer. Therefore, the dummy wafer will not be oxidized during thermal oxidation, thereby reducing dummy wafer consumption, decreasing production cost, avoiding particulate matter produced due to oxidation of the dummy wafer, and preventing the wafer to be oxidized from contamination.
摘要翻译：提供一种半导体制造方法，其中保护层沉积在伪晶片上，使得保护层完全包住虚设晶片。因此，在热氧化期间，伪晶片不会被氧化，从而减少了虚设晶片消耗，降低了生产成本，避免了由于虚设晶片的氧化而产生的颗粒物质，并且防止晶片被污染而被氧化。

3. 发明申请

US20150035087A1 Method for Manufacturing Dummy Gate in Gate-Last Process and Dummy Gate in Gate-Last Process 有权
标题翻译：闸门最后过程中虚拟门制造方法及闸门最后过程中虚拟门的制作方法
公开(公告)号：US20150035087A1
公开(公告)日：2015-02-05
申请号：US14119864
申请日：2012-12-12
申请人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
发明人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
IPC分类号： H01L29/66 , H01L29/51 , H01L29/423
CPC分类号： H01L29/66545 , H01L21/28123 , H01L29/42364 , H01L29/513 , H01L29/518
摘要： A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.
摘要翻译：提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成光致抗蚀剂线，并修整所形成的光致抗蚀剂线，使得修整的光致抗蚀剂线的宽度小于或等于22nm; 并根据修整的光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层无定形硅。

4. 发明申请

US20140332958A1 Method for Manufacturing Dummy Gate in Gate-Last Process and Dummy Gate in Gate-Last Process 有权
标题翻译：闸门最后过程中虚拟门制造方法及闸门最后过程中虚拟门的制作方法
公开(公告)号：US20140332958A1
公开(公告)日：2014-11-13
申请号：US14119862
申请日：2012-12-12
申请人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
发明人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/2807 , H01L21/28123 , H01L29/4232 , H01L29/78
摘要： A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer α-Si. Correspondingly, a dummy gate in a gate-last process is also provided.
摘要翻译：提供了一种在门最后工艺中制造虚拟栅极的方法。该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成宽度范围为32nm至45nm的光致抗蚀剂线; 根据光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层α- Si。相应地，还提供了最后进程中的虚拟门。

5. 发明授权

US08834155B2 Wafer transfer apparatus and wafer transfer method 有权
标题翻译：晶圆转印装置和晶片转印方法
公开(公告)号：US08834155B2
公开(公告)日：2014-09-16
申请号：US13140471
申请日：2011-04-11
申请人： Chunlong Li , Junfeng Li
发明人： Chunlong Li , Junfeng Li
IPC分类号： F27D15/02 , H01L21/677 , H01L21/67
CPC分类号： H01L21/67766 , H01L21/67109 , H01L21/67778
摘要： A water transfer apparatus and a wafer transfer method are provided. The wafer transfer apparatus is provided with a heating component and a cooling component, the heating component heats the wafer carrying component to a temperature the same as the wafer when it is just unloaded from the rapid thermal anneal tool, and the cooling component cools the wafer carrying component along with the wafer to room temperature, thereby avoiding the large temperature difference between the wafer and the wafer transfer apparatus, preventing the high thermal stress induced inside the wafer during wafer transfer, avoiding wafer breakage, and ensuring the completeness of the wafer.
摘要翻译：提供了一种输水装置和晶片转印方法。晶片传送装置设置有加热部件和冷却部件，当刚刚从快速热退火工具卸载时，加热部件将晶片承载部件加热到与晶片相同的温度，并且冷却部件冷却晶片携带部件与晶片一起至室温，从而避免晶片和晶片传送装置之间的温差大，防止晶片转印期间在晶片内引起的高热应力，避免晶片断裂，并确保晶片的完整性。

6. 发明申请

US20120247723A1 WAFER TRANSFER APPARATUS AND WAFER TRANSFER METHOD 有权
标题翻译： WAFER传输设备和传输方法
公开(公告)号：US20120247723A1
公开(公告)日：2012-10-04
申请号：US13140471
申请日：2011-04-11
申请人： Chunlong Li , Junfeng Li
发明人： Chunlong Li , Junfeng Li
IPC分类号： B25J11/00 , F25B29/00
CPC分类号： H01L21/67766 , H01L21/67109 , H01L21/67778
摘要： A water transfer apparatus and a wafer transfer method are provided. The wafer transfer apparatus is provided with a heating component and a cooling component, the heating component heats the wafer carrying component to a temperature the same as the wafer when it is just unloaded from the rapid thermal anneal tool, and the cooling component cools the wafer carrying component along with the wafer to room temperature, thereby avoiding the large temperature difference between the wafer and the wafer transfer apparatus, preventing the high thermal stress induced inside the wafer during wafer transfer, avoiding wafer breakage, and ensuring the completeness of the wafer.
摘要翻译：提供了一种输水装置和晶片转印方法。晶片传送装置设置有加热部件和冷却部件，当刚刚从快速热退火工具卸载时，加热部件将晶片承载部件加热到与晶片相同的温度，并且冷却部件冷却晶片携带部件与晶片一起至室温，从而避免晶片和晶片传送装置之间的温差大，防止晶片转印期间在晶片内引起的高热应力，避免晶片断裂，并确保晶片的完整性。

7. 发明授权

US09202890B2 Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process 有权
标题翻译：最后一个进程中的伪栅极的制造方法和栅极最后工艺中的虚拟栅极的制造方法
公开(公告)号：US09202890B2
公开(公告)日：2015-12-01
申请号：US14119862
申请日：2012-12-12
申请人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
发明人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
IPC分类号： H01L21/8249 , H01L29/66 , H01L21/28 , H01L29/78 , H01L29/423
CPC分类号： H01L29/66545 , H01L21/2807 , H01L21/28123 , H01L29/4232 , H01L29/78
摘要： A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer α-Si. Correspondingly, a dummy gate in a gate-last process is also provided.
摘要翻译：提供了一种在门最后工艺中制造虚拟栅极的方法。该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成宽度为32nm至45nm的光致抗蚀剂线; 根据光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层α- Si。相应地，还提供了最后进程中的虚拟门。

8. 发明申请

US20130061884A1 METHOD FOR CLEANING WAFER AFTER CHEMICAL MECHANICAL PLANARIZATION 审中-公开
标题翻译：化学机械平面清洗方法
公开(公告)号：US20130061884A1
公开(公告)日：2013-03-14
申请号：US13641874
申请日：2012-03-23
申请人： Tao Yang , Chao Zhao , Junfeng Li
发明人： Tao Yang , Chao Zhao , Junfeng Li
IPC分类号： B08B3/04
CPC分类号： H01L21/67051
摘要： A method for cleaning wafer after chemical mechanical planarization that includes placing the wafer in the wafer holder and rotating the wafer holder and the wafer simultaneously, cleaning with chemicals by providing the wafer surface with chemical detergent through the detergent supply cantilever that keeps a certain distance away from the wafer surface, cleaning with deionized water by providing the wafer surface with deionized water through the detergent supply cantilever to remove the chemical detergent and cleaning products. The method also includes the second clean for better cleaning effect and drying the wafer out. According to the wafer cleaning method, the non-contact detergent and deionized water supply cantilever used for wafer cleaning reduces or eliminates the possible problems in making macro scratches on wafer surface in the scrubbing process and increases the yield for wafer devices.
摘要翻译：一种用于在化学机械平面化之后清洁晶片的方法，包括将晶片放置在晶片保持器中并同时旋转晶片保持器和晶片，用化学药剂清洗通过在一定距离之外的洗涤剂供给悬臂的化学清洁剂从晶片表面，用去离子水清洗，通过提供晶片表面的去离子水通过洗涤剂供应悬臂来去除化学清洁剂和清洁产品。该方法还包括第二次清洁以获得更好的清洁效果并干燥晶片。根据晶片清洗方法，用于晶片清洗的非接触式洗涤剂和去离子水供应悬臂减少或消除了在洗涤过程中在晶片表面上产生宏观划痕的可能问题，并提高了晶片装置的产量。

9. 发明申请

US20130059434A1 METHOD FOR MANUFACTURING ELECTRODES AND WIRES IN GATE LAST PROCESS 审中-公开
标题翻译：在门过程中制造电极和电线的方法
公开(公告)号：US20130059434A1
公开(公告)日：2013-03-07
申请号：US13509722
申请日：2011-11-29
申请人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Xiaobin He , Yihong Lu
发明人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Xiaobin He , Yihong Lu
IPC分类号： H01L21/28
CPC分类号： H01L29/66606 , H01L21/28518 , H01L21/76802 , H01L21/7684 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/78
摘要： The present invention provides a method for manufacturing a gate electrode and a contact wire simultaneously in a gate last process, comprising the steps of: forming a gate trench in an inter layer dielectric layer on a substrate; forming a filling layer in the gate trench and on the inter layer dielectric layer; etching the filling layer and the inter layer dielectric layer to expose the substrate, to thereby form a source/drain contact hole; removing the filling layer to expose the gate trench and the source/drain contact hole; forming metal silicide in the source/drain contact hole; depositing a gate dielectric layer and a metal gate in the gate trench; filling metal in the gate trench and the source/drain contact hole; and planarizing the filled metal. In accordance with the manufacturing method of the present invention, the gate electrode wire will be made of the same metal material as the contact hole such that the two can be manufactured by one CMP process. Such a design has the advantages of simplifying complexity of process integration on one hand and greatly strengthening control of defects by CMP process on the other hand, thereby avoiding the defects like erosion and dishing that may be produced between different metal materials.
摘要翻译：本发明提供了一种用于在栅极最后工艺中同时制造栅电极和接触导线的方法，包括以下步骤：在衬底上的层间电介质层中形成栅极沟槽; 在栅极沟槽和层间电介质层上形成填充层; 蚀刻填充层和层间电介质层以暴露衬底，从而形成源极/漏极接触孔; 去除填充层以暴露栅极沟槽和源极/漏极接触孔; 在源极/漏极接触孔中形成金属硅化物; 在栅极沟槽中沉积栅极电介质层和金属栅极; 在栅极沟槽和源极/漏极接触孔中填充金属; 并平坦化填充的金属。根据本发明的制造方法，栅极电极线将由与接触孔相同的金属材料制成，使得两者可以通过一个CMP工艺制造。这样的设计一方面简化了工艺集成的复杂性，另一方面通过CMP工艺大大加强了缺陷的控制，从而避免了不同金属材料之间可能产生的侵蚀和凹陷等缺陷。

10. 发明申请

US20080159559A1 Post-filter for microphone array 审中-公开
标题翻译：麦克风阵列的后置滤波器
公开(公告)号：US20080159559A1
公开(公告)日：2008-07-03
申请号：US12074085
申请日：2008-02-29
申请人： Masato Akagi , Junfeng Li , Masaaki Uechi , Kazuya Sasaki
发明人： Masato Akagi , Junfeng Li , Masaaki Uechi , Kazuya Sasaki
IPC分类号： H04R3/00
CPC分类号： G10L21/0208 , G10L2021/02166 , H04R3/005
摘要： A post-filter includes a microphone array including at least two microphones to which a voice signal are input, a beam former which forms the voice signal input from the microphone array, a divider which divides a target sound containing noise input from the microphone array into at least two frequency bands at a predetermined frequency, a first filter which estimates the filter gain with the noise non-correlated between the microphones, a second filter which estimates a filter gain of one microphone of the microphone array or an average signal of the microphone array, an adder which adds the outputs from the first and second filters to each other, and a filter for reducing the noise based on the outputs from the adder and the beam former.
摘要翻译：后置滤波器包括麦克风阵列，其包括输入语音信号的至少两个麦克风，形成从麦克风阵列输入的语音信号的波束形成器，将包含来自麦克风阵列的噪声输入的目标声音分成以预定频率的至少两个频带，第一滤波器，其利用麦克风之间不相关的噪声来估计滤波器增益;估计麦克风阵列的一个麦克风的滤波器增益的第二滤波器或麦克风的平均信号阵列，将来自第一和第二滤波器的输出彼此相加的加法器，以及用于基于来自加法器和波束形成器的输出来降低噪声的滤波器。

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