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1. 发明授权

US08643404B1 Self-calibration of output buffer driving strength 有权
标题翻译：输出缓冲器自校准驱动强度
公开(公告)号：US08643404B1
公开(公告)日：2014-02-04
申请号：US13556579
申请日：2012-07-24
申请人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen
发明人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen
IPC分类号： H03K3/00
CPC分类号： H03K17/145 , H03K19/00384 , H03K2005/00026
摘要： An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.
摘要翻译：集成电路包括输出缓冲器和控制电路。输出缓冲器具有信号输入，信号输出和一组控制输入。输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。控制电路连接到输出缓冲器的一组控制输入。控制电路使用第一和第二定时信号来产生控制信号，并且包括产生具有参考延迟的第一定时信号的参考延迟电路，以及延迟仿真电路，其产生与第二定时信号相关的仿真延迟输出缓冲区延迟。

2. 发明授权

US08825978B2 Memory apparatus 有权
标题翻译：存储设备
公开(公告)号：US08825978B2
公开(公告)日：2014-09-02
申请号：US13584393
申请日：2012-08-13
申请人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
发明人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
IPC分类号： G06F12/00 , G06F13/42 , G11C29/00
CPC分类号： G11C7/1072 , G11C7/1066 , G11C7/222 , G11C2207/104
摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.
摘要翻译：存储装置包括主机装置和从装置。主机设备存储验证数据。从设备包括存储单元，控制单元和逻辑单元。控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。前导码数据和存储数据根据内部时钟信号发送。主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。

3. 发明申请

US20140028367A1 SELF-CALIBRATION OF OUTPUT BUFFER DRIVING STRENGTH 有权
标题翻译：自动校准输出缓冲器驱动强度
公开(公告)号：US20140028367A1
公开(公告)日：2014-01-30
申请号：US13556579
申请日：2012-07-24
申请人： YU-MENG CHAUNG , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen
发明人： YU-MENG CHAUNG , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen
IPC分类号： H03K5/06
CPC分类号： H03K17/145 , H03K19/00384 , H03K2005/00026
摘要： An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.
摘要翻译：集成电路包括输出缓冲器和控制电路。输出缓冲器具有信号输入，信号输出和一组控制输入。输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。控制电路连接到输出缓冲器的一组控制输入。控制电路使用第一和第二定时信号来产生控制信号，并且包括产生具有参考延迟的第一定时信号的参考延迟电路，以及延迟仿真电路，其产生与第二定时信号相关的仿真延迟输出缓冲区延迟。

4. 发明申请

US20130326184A1 MEMORY APPARATUS 有权
标题翻译：记忆装置
公开(公告)号：US20130326184A1
公开(公告)日：2013-12-05
申请号：US13584393
申请日：2012-08-13
申请人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
发明人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
IPC分类号： G06F12/00
CPC分类号： G11C7/1072 , G11C7/1066 , G11C7/222 , G11C2207/104
摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.
摘要翻译：存储装置包括主机装置和从装置。主机设备存储验证数据。从设备包括存储器单元，控制单元和逻辑单元。控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。前导码数据和存储数据根据内部时钟信号发送。主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。

5. 发明授权

US08929139B2 Method and apparatus for leakage suppression in flash memory 有权
标题翻译：闪存中泄漏抑制的方法和装置
公开(公告)号：US08929139B2
公开(公告)日：2015-01-06
申请号：US13308301
申请日：2011-11-30
申请人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
发明人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
IPC分类号： G11C11/34 , G11C16/04 , G11C16/34 , G11C11/56 , G11C16/14
CPC分类号： G11C16/3409 , G11C11/5635 , G11C16/0483 , G11C16/14
摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression process includes determining that a given block of memory cells includes one or more over-erased memory cells. Upon the determination, the leakage-suppression process also includes performing a soft program operation to increase the threshold voltage of the over-erased memory cells in the given block.
摘要翻译：本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。在一个实施例中，描述了一种闪存器件，其包括包括多个存储器单元块的存储器阵列。该装置还包括执行泄漏抑制处理的控制器。泄漏抑制过程包括确定给定的存储单元块包括一个或多个过擦除存储器单元。在确定时，泄漏抑制处理还包括执行软程序操作以增加给定块中的被擦除的存储器单元的阈值电压。

6. 发明授权

US08723559B2 Dynamic driver circuit 有权
标题翻译：动态驱动电路
公开(公告)号：US08723559B2
公开(公告)日：2014-05-13
申请号：US13603815
申请日：2012-09-05
申请人： Chang-Ting Chen , Chin-Hung Chang , Shang-Chi Yang , Kuan-Ming Lu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Chang-Ting Chen , Chin-Hung Chang , Shang-Chi Yang , Kuan-Ming Lu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： G11C8/08 , G11C16/08
摘要： A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.
摘要翻译：可用作字线驱动器的电路包括响应于控制节点上的电压而切换的驱动器，以及向控制节点提供电压的电路。向控制节点施加电压的电路提供趋向于将控制节点拉至第一源电压的第一静态电流，并且响应于选择驱动器的信号提供战斗电流脉冲以将控制节点向下拉到第二静态电流源电压，克服第一静电流。此外，电路在选择驱动器的信号转变时提供上拉升压电流，该信号使关闭电流消失，并且向控制节点施加升压电流脉冲，以帮助快速将控制节点拉到第一源电压。

7. 发明申请

US20140062543A1 DYNAMIC DRIVER CIRCUIT 有权
标题翻译：动力驱动电路
公开(公告)号：US20140062543A1
公开(公告)日：2014-03-06
申请号：US13603815
申请日：2012-09-05
申请人： Chang-Ting Chen , Chin-Hung Chang , Shang-Chi Yang , Kuan-Ming Lu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Chang-Ting Chen , Chin-Hung Chang , Shang-Chi Yang , Kuan-Ming Lu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： H03K3/00
CPC分类号： G11C8/08 , G11C16/08
摘要： A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.
摘要翻译：可用作字线驱动器的电路包括响应于控制节点上的电压而切换的驱动器，以及向控制节点提供电压的电路。向控制节点施加电压的电路提供趋向于将控制节点拉至第一源电压的第一静态电流，并且响应于选择驱动器的信号提供战斗电流脉冲以将控制节点向下拉到第二静态电流源电压，克服第一静电流。此外，电路在选择驱动器的信号转变时提供上拉升压电流，该信号使关闭电流消失，并且向控制节点施加升压电流脉冲，以帮助快速将控制节点拉到第一源电压。

8. 发明授权

US08638636B2 Word line decoder circuit apparatus and method 有权
标题翻译：字线解码电路装置及方法
公开(公告)号：US08638636B2
公开(公告)日：2014-01-28
申请号：US12816960
申请日：2010-06-16
申请人： Shin-Jang Shen , Bo-Chang Wu , Chuan Ying Yu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Shin-Jang Shen , Bo-Chang Wu , Chuan Ying Yu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C8/00
CPC分类号： G11C16/16
摘要： One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.
摘要翻译：该技术的一个实施例是一种装置，存储器集成电路。存储器集成电路具有字线地址解码电路。该电路允许选择单个字线以具有擦除电压。解码器电路包括反相器和逻辑。逆变器具有输入和控制字线的输出以执行擦除操作。输入的电压范围在第一参考电压和第二电压基准之间延伸。电压基准的示例是电压源和地。在一些实施例中，该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。解码器的逻辑电路由字线地址控制，以在擦除操作期间确定反相器的输入值。

9. 发明授权

US08374007B2 Supplying power with maintaining its output power signal with the assistance of another power apply and method therefor 有权
标题翻译：在另一种电源的协助下，通过维持其输出功率信号来提供电力及其方法
公开(公告)号：US08374007B2
公开(公告)日：2013-02-12
申请号：US12820422
申请日：2010-06-22
申请人： Chih-Ting Hu , Chun-Hsiung Hung , Chuan-Ying Yu , Wu-Chin Peng , Kuen-Long Chang , Ken-Hui Chen
发明人： Chih-Ting Hu , Chun-Hsiung Hung , Chuan-Ying Yu , Wu-Chin Peng , Kuen-Long Chang , Ken-Hui Chen
IPC分类号： H02M7/25 , H02M7/00
CPC分类号： H02M3/07 , G11C5/145 , H02M2001/0032 , Y02B70/16
摘要： A power supply apparatus and a method for supplying power are provided. The apparatus, for use in a system having a first power signal, includes an assistance unit and a power supply device. The assistance unit outputs at least one maintaining signal according to the first power signal selectively. The power supply device outputs a second power signal, wherein the power supply device maintains the second power signal according to the at least one maintaining signal, for example, in an inactive state, such as an idle or standby state or other suitable timing.
摘要翻译：提供电源装置和供电方法。用于具有第一功率信号的系统中的装置包括辅助单元和电源装置。辅助单元选择性地输出根据第一功率信号的至少一个维持信号。电源装置输出第二电力信号，其中电源装置根据至少一个维持信号维持第二电力信号，例如处于非空闲状态，例如空闲或待机状态或其他合适的定时。

10. 发明申请

US20110317493A1 Method and Apparatus of Performing An Erase Operation on a Memory Integrated Circuit 有权
标题翻译：在存储器集成电路上执行擦除操作的方法和装置
公开(公告)号：US20110317493A1
公开(公告)日：2011-12-29
申请号：US12826280
申请日：2010-06-29
申请人： Yi-Fan Chang , Su-chueh Lo , Cheng Ming Yih , Ta Kang Chu , Chu Ching Wu , Kuo Yu Liao , Ken Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yi-Fan Chang , Su-chueh Lo , Cheng Ming Yih , Ta Kang Chu , Chu Ching Wu , Kuo Yu Liao , Ken Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C11/5635 , G11C16/0483 , G11C16/3418
摘要： Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.
摘要翻译：各种讨论的方法改进了过度擦除问题和耦合效应，并且包括（A）（i）擦除组的第一外部选定字线之间的多电平接触，以及（ii）与易失性组相邻的第一未选择字线第一外选字线; （B）在（i）擦除组的第一外部选择字线之间的足够的间隔距离，和（ii）与第一外部选择字线相邻的容易组之外的第一未选择字线。这些是将（i）擦除组的第一外部选择的字线从（ii）与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

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