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1. 发明授权

US08643404B1 Self-calibration of output buffer driving strength 有权
标题翻译：输出缓冲器自校准驱动强度
公开(公告)号：US08643404B1
公开(公告)日：2014-02-04
申请号：US13556579
申请日：2012-07-24
申请人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen
发明人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen
IPC分类号： H03K3/00
CPC分类号： H03K17/145 , H03K19/00384 , H03K2005/00026
摘要： An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.
摘要翻译：集成电路包括输出缓冲器和控制电路。输出缓冲器具有信号输入，信号输出和一组控制输入。输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。控制电路连接到输出缓冲器的一组控制输入。控制电路使用第一和第二定时信号来产生控制信号，并且包括产生具有参考延迟的第一定时信号的参考延迟电路，以及延迟仿真电路，其产生与第二定时信号相关的仿真延迟输出缓冲区延迟。

2. 发明授权

US08825978B2 Memory apparatus 有权
标题翻译：存储设备
公开(公告)号：US08825978B2
公开(公告)日：2014-09-02
申请号：US13584393
申请日：2012-08-13
申请人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
发明人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
IPC分类号： G06F12/00 , G06F13/42 , G11C29/00
CPC分类号： G11C7/1072 , G11C7/1066 , G11C7/222 , G11C2207/104
摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.
摘要翻译：存储装置包括主机装置和从装置。主机设备存储验证数据。从设备包括存储单元，控制单元和逻辑单元。控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。前导码数据和存储数据根据内部时钟信号发送。主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。

3. 发明申请

US20140028367A1 SELF-CALIBRATION OF OUTPUT BUFFER DRIVING STRENGTH 有权
标题翻译：自动校准输出缓冲器驱动强度
公开(公告)号：US20140028367A1
公开(公告)日：2014-01-30
申请号：US13556579
申请日：2012-07-24
申请人： YU-MENG CHAUNG , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen
发明人： YU-MENG CHAUNG , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen
IPC分类号： H03K5/06
CPC分类号： H03K17/145 , H03K19/00384 , H03K2005/00026
摘要： An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.
摘要翻译：集成电路包括输出缓冲器和控制电路。输出缓冲器具有信号输入，信号输出和一组控制输入。输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。控制电路连接到输出缓冲器的一组控制输入。控制电路使用第一和第二定时信号来产生控制信号，并且包括产生具有参考延迟的第一定时信号的参考延迟电路，以及延迟仿真电路，其产生与第二定时信号相关的仿真延迟输出缓冲区延迟。

4. 发明申请

US20130326184A1 MEMORY APPARATUS 有权
标题翻译：记忆装置
公开(公告)号：US20130326184A1
公开(公告)日：2013-12-05
申请号：US13584393
申请日：2012-08-13
申请人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
发明人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
IPC分类号： G06F12/00
CPC分类号： G11C7/1072 , G11C7/1066 , G11C7/222 , G11C2207/104
摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.
摘要翻译：存储装置包括主机装置和从装置。主机设备存储验证数据。从设备包括存储器单元，控制单元和逻辑单元。控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。前导码数据和存储数据根据内部时钟信号发送。主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。

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