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1. 发明授权

US08259510B2 Disturb-free static random access memory cell 有权
标题翻译：无噪音静态随机存取存储单元
公开(公告)号：US08259510B2
公开(公告)日：2012-09-04
申请号：US12772238
申请日：2010-05-03
申请人： Ching-Te Chuang , Hao-I Yang , Jihi-Yu Lin , Shyh-Chyi Yang , Ming-Hsien Tu , Wei Hwang , Shyh-Jye Jou , Kun-Ti Lee , Hung-Yu Li
发明人： Ching-Te Chuang , Hao-I Yang , Jihi-Yu Lin , Shyh-Chyi Yang , Ming-Hsien Tu , Wei Hwang , Shyh-Jye Jou , Kun-Ti Lee , Hung-Yu Li
IPC分类号： G11C7/00
CPC分类号： G11C11/412
摘要： A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.
摘要翻译：无干扰的静态随机存取存储单元包括：具有第一接入终端和第二接入终端的锁存电路; 第一切换电路，具有耦合到第一接入终端的第一比特传送终端，耦合到第一写字线的第一控制终端和第二比特传送终端; 第二切换电路，具有耦合到第二接入终端的第三比特传送终端，耦合到第二写字线的第二控制终端，以及耦合到第二比特传送终端的第四比特传送终端。第三开关电路，具有耦合到第四位转移终端的第五位转移终端，耦合到字线的第三控制端和耦合到位线的第六位转移端; 以及耦合到位线的感测放大器，用于确定出现在位线处的位值。

2. 发明申请

US20110128796A1 DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL 有权
标题翻译：无干扰的静态随机存取存储器单元
公开(公告)号：US20110128796A1
公开(公告)日：2011-06-02
申请号：US12772238
申请日：2010-05-03
申请人： Ching-Te Chuang , Hao-I Yang , Jihi-Yu Lin , Shyh-Chyi Yang , Ming-Hsien Tu , Wei Hwang , Shyh-Jye Jou , Kun-Ti Lee , Hung-Yu Li
发明人： Ching-Te Chuang , Hao-I Yang , Jihi-Yu Lin , Shyh-Chyi Yang , Ming-Hsien Tu , Wei Hwang , Shyh-Jye Jou , Kun-Ti Lee , Hung-Yu Li
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C11/412
摘要： A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.
摘要翻译：无干扰的静态随机存取存储单元包括：具有第一接入终端和第二接入终端的锁存电路; 第一切换电路，具有耦合到第一接入终端的第一比特传送终端，耦合到第一写字线的第一控制终端和第二比特传送终端; 第二切换电路，具有耦合到第二接入终端的第三比特传送终端，耦合到第二写字线的第二控制终端，以及耦合到第二比特传送终端的第四比特传送终端。第三开关电路，具有耦合到第四位转移终端的第五位转移终端，耦合到字线的第三控制端和耦合到位线的第六位转移端; 以及耦合到位线的感测放大器，用于确定出现在位线处的位值。

3. 发明授权

US08325512B2 SRAM writing system and related apparatus 有权
标题翻译： SRAM写入系统及相关设备
公开(公告)号：US08325512B2
公开(公告)日：2012-12-04
申请号：US13070977
申请日：2011-03-24
申请人： Ching-Te Chuang , Wei-Chiang Shih , Hung-Yu Lee , Jihi-Yu Lin , Ming-Hsien Tu , Shyh-Jye Jou , Kun-Di Lee
发明人： Ching-Te Chuang , Wei-Chiang Shih , Hung-Yu Lee , Jihi-Yu Lin , Ming-Hsien Tu , Shyh-Jye Jou , Kun-Di Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.
摘要翻译：提供了SRAM写入系统和相关装置。本发明的写入系统具有虚拟副本写入电路，负脉冲控制器和至少一个正常写入电路; 每个正常写入电路包括写入驱动器和负脉冲供应器。在写入时，虚拟副本写入电路驱动虚拟副本位线，使得负脉冲控制器根据虚拟副本位线的电平产生负脉冲控制信号。在每个写入电路中，当写入驱动器将相关联的位线连接到用于驱动电平转换的偏置端时，负脉冲供应器根据接收到的负值将偏置端从工作电压切换到不同的负脉冲电压脉冲控制信号。

4. 发明申请

US20110235444A1 SRAM WRITING SYSTEM AND RELATED APPARATUS 有权
标题翻译： SRAM写入系统及相关设备
公开(公告)号：US20110235444A1
公开(公告)日：2011-09-29
申请号：US13070977
申请日：2011-03-24
申请人： Ching-Te Chuang , Wei-Chiang Shih , Hung-Yu Lee , Jihi-Yu Lin , Ming-Hsien Tu , Shyh-Jye Jou , Kun-Di Lee
发明人： Ching-Te Chuang , Wei-Chiang Shih , Hung-Yu Lee , Jihi-Yu Lin , Ming-Hsien Tu , Shyh-Jye Jou , Kun-Di Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.
摘要翻译：提供SRAM写入系统及相关装置。本发明的写入系统具有虚拟副本写入电路，负脉冲控制器和至少一个正常写入电路; 每个正常写入电路包括写入驱动器和负脉冲供应器。在写入时，虚拟副本写入电路驱动虚拟副本位线，使得负脉冲控制器根据虚拟副本位线的电平产生负脉冲控制信号。在每个写入电路中，当写入驱动器将相关联的位线连接到用于驱动电平转换的偏置端时，负脉冲供应器根据接收到的负值将偏置端从工作电压切换到不同的负脉冲电压脉冲控制信号。

5. 发明申请

US20120327704A1 SEMICONDUCTOR MEMORIES 有权
标题翻译：半导体记忆
公开(公告)号：US20120327704A1
公开(公告)日：2012-12-27
申请号：US13164807
申请日：2011-06-21
申请人： Wei Min CHAN , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
发明人： Wei Min CHAN , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.
摘要翻译：半导体存储器包括具有形成锁存器的第一和反相器的位单元。第一和第二晶体管分别耦合到锁存器的第一和第二存储节点以及第一和第二写入位线。第一和第二晶体管中的每一个具有耦合到第一节点的相应栅极。第三和第四晶体管在第一节点处串联耦合在一起，并且设置在写入字线和第一电压源之间。第一和第二晶体管中的每一个具有耦合到第一控制线的相应栅极。第五晶体管具有耦合到第二电压源的源极，耦合到锁存器的至少一个反相器的漏极和耦合到第一节点的栅极。读端口耦合到第一读位线和锁存器的第二存储节点。

6. 发明授权

US08576655B2 Semiconductor memories 有权
标题翻译：半导体存储器
公开(公告)号：US08576655B2
公开(公告)日：2013-11-05
申请号：US13164807
申请日：2011-06-21
申请人： Wei Min Chan , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
发明人： Wei Min Chan , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
IPC分类号： G11C8/00
CPC分类号： G11C11/412
摘要： A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.
摘要翻译：半导体存储器包括具有形成锁存器的第一和反相器的位单元。第一和第二晶体管分别耦合到锁存器的第一和第二存储节点以及第一和第二写入位线。第一和第二晶体管中的每一个具有耦合到第一节点的相应栅极。第三和第四晶体管在第一节点处串联耦合在一起，并且设置在写入字线和第一电压源之间。第一和第二晶体管中的每一个具有耦合到第一控制线的相应栅极。第五晶体管具有耦合到第二电压源的源极，耦合到锁存器的至少一个反相器的漏极和耦合到第一节点的栅极。读端口耦合到第一读位线和锁存器的第二存储节点。

7. 发明申请

US20120195106A1 SRAM Timing Cell Apparatus and Methods 有权
标题翻译： SRAM定时单元设备和方法
公开(公告)号：US20120195106A1
公开(公告)日：2012-08-02
申请号：US13017793
申请日：2011-01-31
申请人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
发明人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
IPC分类号： G11C11/40 , G11C7/06
CPC分类号： G11C7/227 , G11C11/418
摘要： Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and coupled in series to provide a signal indicating the SRAM tracking time. Methods for SRAM timing are disclosed.
摘要翻译：公开了用于提供SRAM定时跟踪单元电路的装置和方法。在一个实施例中，一种装置包括一个SRAM阵列，它包括排列成行和列的静态随机存取存储单元; 多条字线，每条字线都沿着一条行与存储器单元耦合; 用于输出时钟信号的时钟发生电路; 字线生成电路，用于响应于所述时钟信号中的一个生成在所述多个字线上的脉冲，并响应于所述时钟信号之一来终止所述脉冲; 以及跟踪单元，用于接收时钟信号并用于在SRAM跟踪时间之后将时钟产生电路输出字线脉冲结束信号; 其中所述跟踪单元还包括位于所述SRAM阵列中并且串联耦合的SRAM跟踪电路，以提供指示所述SRAM跟踪时间的信号。公开了SRAM定时的方法。

8. 发明授权

US08644087B2 Leakage-aware keeper for semiconductor memory 有权
标题翻译：用于半导体存储器的漏电保护器
公开(公告)号：US08644087B2
公开(公告)日：2014-02-04
申请号：US13177711
申请日：2011-07-07
申请人： Jihi-Yu Lin , Li-Wen Wang , Wei Min Chan , Yen-Huei Chen
发明人： Jihi-Yu Lin , Li-Wen Wang , Wei Min Chan , Yen-Huei Chen
IPC分类号： G11C7/10
CPC分类号： G11C7/04 , G11C11/417
摘要： A circuit includes a first circuit configured to sense a leakage of a first bit line and output a first signal in response, and a second circuit configured to receive the first signal output from the first circuit and in response supply current to a second bit line for maintaining a voltage level of the second bit line.
摘要翻译：电路包括被配置为感测第一位线的泄漏并响应地输出第一信号的第一电路，以及被配置为接收从第一电路输出的第一信号并响应于向第二位线提供电流的第二电路，维持第二位线的电压电平。

9. 发明授权

US08477527B2 SRAM timing cell apparatus and methods 有权
标题翻译： SRAM定时单元装置和方法
公开(公告)号：US08477527B2
公开(公告)日：2013-07-02
申请号：US13017793
申请日：2011-01-31
申请人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
发明人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
IPC分类号： G11C11/00
CPC分类号： G11C7/227 , G11C11/418
摘要： Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and coupled in series to provide a signal indicating the SRAM tracking time. Methods for SRAM timing are disclosed.
摘要翻译：公开了用于提供SRAM定时跟踪单元电路的装置和方法。在一个实施例中，一种装置包括一个SRAM阵列，它包括排列成行和列的静态随机存取存储单元; 多条字线，每条字线都沿着一条行与存储器单元耦合; 用于输出时钟信号的时钟发生电路; 字线生成电路，用于响应于所述时钟信号中的一个生成在所述多个字线上的脉冲，并响应于所述时钟信号之一来终止所述脉冲; 以及跟踪单元，用于接收时钟信号并用于在SRAM跟踪时间之后将时钟产生电路输出字线脉冲结束信号; 其中所述跟踪单元还包括位于所述SRAM阵列中并且串联耦合的SRAM跟踪电路，以提供指示所述SRAM跟踪时间的信号。公开了SRAM定时的方法。

10. 发明授权

US08441885B2 Methods and apparatus for memory word line driver 有权
标题翻译：内存字线驱动程序的方法和装置
公开(公告)号：US08441885B2
公开(公告)日：2013-05-14
申请号：US13051681
申请日：2011-03-18
申请人： Wei Min Chan , Li-Wen Wang , Jihi-Yu Lin , Chen-Lin Yang , Shao-Yu Chou
发明人： Wei Min Chan , Li-Wen Wang , Jihi-Yu Lin , Chen-Lin Yang , Shao-Yu Chou
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C8/18 , G11C11/413
摘要： A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.
摘要翻译：公开了一种字线驱动电路及相应的方法。一种装置，包括被耦合以接收地址输入并具有解码器输出的解码器电路; 以及字线时钟选通电路，其耦合到所述解码器输出和字线时钟信号，被配置为响应于所述字线时钟信号上的边沿选择性地输出字线信号; 其中所述地址输入具有相对于所述字线时钟信号的边缘的建立时间要求，并且所述地址输入相对于所述字线时钟信号的边缘具有零或更小的保持时间要求。公开了从字线驱动器提供字线信号的方法。

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