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1. 发明申请

US20120195106A1 SRAM Timing Cell Apparatus and Methods 有权
标题翻译： SRAM定时单元设备和方法
公开(公告)号：US20120195106A1
公开(公告)日：2012-08-02
申请号：US13017793
申请日：2011-01-31
申请人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
发明人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
IPC分类号： G11C11/40 , G11C7/06
CPC分类号： G11C7/227 , G11C11/418
摘要： Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and coupled in series to provide a signal indicating the SRAM tracking time. Methods for SRAM timing are disclosed.
摘要翻译：公开了用于提供SRAM定时跟踪单元电路的装置和方法。在一个实施例中，一种装置包括一个SRAM阵列，它包括排列成行和列的静态随机存取存储单元; 多条字线，每条字线都沿着一条行与存储器单元耦合; 用于输出时钟信号的时钟发生电路; 字线生成电路，用于响应于所述时钟信号中的一个生成在所述多个字线上的脉冲，并响应于所述时钟信号之一来终止所述脉冲; 以及跟踪单元，用于接收时钟信号并用于在SRAM跟踪时间之后将时钟产生电路输出字线脉冲结束信号; 其中所述跟踪单元还包括位于所述SRAM阵列中并且串联耦合的SRAM跟踪电路，以提供指示所述SRAM跟踪时间的信号。公开了SRAM定时的方法。

2. 发明授权

US08644087B2 Leakage-aware keeper for semiconductor memory 有权
标题翻译：用于半导体存储器的漏电保护器
公开(公告)号：US08644087B2
公开(公告)日：2014-02-04
申请号：US13177711
申请日：2011-07-07
申请人： Jihi-Yu Lin , Li-Wen Wang , Wei Min Chan , Yen-Huei Chen
发明人： Jihi-Yu Lin , Li-Wen Wang , Wei Min Chan , Yen-Huei Chen
IPC分类号： G11C7/10
CPC分类号： G11C7/04 , G11C11/417
摘要： A circuit includes a first circuit configured to sense a leakage of a first bit line and output a first signal in response, and a second circuit configured to receive the first signal output from the first circuit and in response supply current to a second bit line for maintaining a voltage level of the second bit line.
摘要翻译：电路包括被配置为感测第一位线的泄漏并响应地输出第一信号的第一电路，以及被配置为接收从第一电路输出的第一信号并响应于向第二位线提供电流的第二电路，维持第二位线的电压电平。

3. 发明授权

US08477527B2 SRAM timing cell apparatus and methods 有权
标题翻译： SRAM定时单元装置和方法
公开(公告)号：US08477527B2
公开(公告)日：2013-07-02
申请号：US13017793
申请日：2011-01-31
申请人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
发明人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
IPC分类号： G11C11/00
CPC分类号： G11C7/227 , G11C11/418
摘要： Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and coupled in series to provide a signal indicating the SRAM tracking time. Methods for SRAM timing are disclosed.
摘要翻译：公开了用于提供SRAM定时跟踪单元电路的装置和方法。在一个实施例中，一种装置包括一个SRAM阵列，它包括排列成行和列的静态随机存取存储单元; 多条字线，每条字线都沿着一条行与存储器单元耦合; 用于输出时钟信号的时钟发生电路; 字线生成电路，用于响应于所述时钟信号中的一个生成在所述多个字线上的脉冲，并响应于所述时钟信号之一来终止所述脉冲; 以及跟踪单元，用于接收时钟信号并用于在SRAM跟踪时间之后将时钟产生电路输出字线脉冲结束信号; 其中所述跟踪单元还包括位于所述SRAM阵列中并且串联耦合的SRAM跟踪电路，以提供指示所述SRAM跟踪时间的信号。公开了SRAM定时的方法。

4. 发明申请

US20130010544A1 LEAKAGE-AWARE KEEPER FOR SEMICONDUCTOR MEMORY 有权
标题翻译：漏电保护器用于半导体存储器
公开(公告)号：US20130010544A1
公开(公告)日：2013-01-10
申请号：US13177711
申请日：2011-07-07
申请人： Jihi-Yu LIN , Li-Wen Wang , Wei Min Chan , Yen-Huei Chen
发明人： Jihi-Yu LIN , Li-Wen Wang , Wei Min Chan , Yen-Huei Chen
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/04 , G11C11/417
摘要： A circuit includes a first circuit configured to sense a leakage of a first bit line and output a first signal in response, and a second circuit configured to receive the first signal output from the first circuit and in response supply current to a second bit line for maintaining a voltage level of the second bit line.
摘要翻译：电路包括被配置为感测第一位线的泄漏并响应地输出第一信号的第一电路，以及被配置为接收从第一电路输出的第一信号并且响应于向第二位线提供电流的第二电路，维持第二位线的电压电平。

5. 发明授权

US08576655B2 Semiconductor memories 有权
标题翻译：半导体存储器
公开(公告)号：US08576655B2
公开(公告)日：2013-11-05
申请号：US13164807
申请日：2011-06-21
申请人： Wei Min Chan , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
发明人： Wei Min Chan , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
IPC分类号： G11C8/00
CPC分类号： G11C11/412
摘要： A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.
摘要翻译：半导体存储器包括具有形成锁存器的第一和反相器的位单元。第一和第二晶体管分别耦合到锁存器的第一和第二存储节点以及第一和第二写入位线。第一和第二晶体管中的每一个具有耦合到第一节点的相应栅极。第三和第四晶体管在第一节点处串联耦合在一起，并且设置在写入字线和第一电压源之间。第一和第二晶体管中的每一个具有耦合到第一控制线的相应栅极。第五晶体管具有耦合到第二电压源的源极，耦合到锁存器的至少一个反相器的漏极和耦合到第一节点的栅极。读端口耦合到第一读位线和锁存器的第二存储节点。

6. 发明授权

US08441885B2 Methods and apparatus for memory word line driver 有权
标题翻译：内存字线驱动程序的方法和装置
公开(公告)号：US08441885B2
公开(公告)日：2013-05-14
申请号：US13051681
申请日：2011-03-18
申请人： Wei Min Chan , Li-Wen Wang , Jihi-Yu Lin , Chen-Lin Yang , Shao-Yu Chou
发明人： Wei Min Chan , Li-Wen Wang , Jihi-Yu Lin , Chen-Lin Yang , Shao-Yu Chou
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C8/18 , G11C11/413
摘要： A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.
摘要翻译：公开了一种字线驱动电路及相应的方法。一种装置，包括被耦合以接收地址输入并具有解码器输出的解码器电路; 以及字线时钟选通电路，其耦合到所述解码器输出和字线时钟信号，被配置为响应于所述字线时钟信号上的边沿选择性地输出字线信号; 其中所述地址输入具有相对于所述字线时钟信号的边缘的建立时间要求，并且所述地址输入相对于所述字线时钟信号的边缘具有零或更小的保持时间要求。公开了从字线驱动器提供字线信号的方法。

7. 发明申请

US20120236675A1 Methods and Apparatus for Memory Word Line Driver 有权
标题翻译：内存字线驱动程序的方法和装置
公开(公告)号：US20120236675A1
公开(公告)日：2012-09-20
申请号：US13051681
申请日：2011-03-18
申请人： Wei Min Chan , Li-Wen Wang , Jihi-Yu Lin , Chen-Lin Yang , Shao-Yu Chou
发明人： Wei Min Chan , Li-Wen Wang , Jihi-Yu Lin , Chen-Lin Yang , Shao-Yu Chou
IPC分类号： G11C8/10
CPC分类号： G11C8/08 , G11C8/18 , G11C11/413
摘要： A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.
摘要翻译：公开了一种字线驱动电路及相应的方法。一种装置，包括被耦合以接收地址输入并具有解码器输出的解码器电路; 以及字线时钟选通电路，其耦合到所述解码器输出和字线时钟信号，被配置为响应于所述字线时钟信号上的边沿选择性地输出字线信号; 其中所述地址输入具有相对于所述字线时钟信号的边缘的建立时间要求，并且所述地址输入相对于所述字线时钟信号的边缘具有零或更小的保持时间要求。公开了从字线驱动器提供字线信号的方法。

8. 发明授权

US08559251B2 Memory circuit and method of writing datum to memory circuit 有权
标题翻译：存储电路和将数据写入存储电路的方法
公开(公告)号：US08559251B2
公开(公告)日：2013-10-15
申请号：US13354884
申请日：2012-01-20
申请人： Chih-Yu Lin , Wei Min Chan , Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
发明人： Chih-Yu Lin , Wei Min Chan , Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G11C7/10
CPC分类号： G11C11/419
摘要： A circuit includes a first node, a second node, a memory cell, a first data line, a second data line, and a write driver. The memory cell is coupled to the first node and the second node and powered by a first voltage at the first node and a second voltage at the second node. The first data line and the second data line are coupled to the memory cell. The write driver has a third node carrying a third voltage less than the first voltage during a write operation. The write deriver is coupled to the first data line and the second data line and configured to, during a write operation, selectively coupling one of the first data line and the second data line to the third node and coupling the other one of the first data line and the second data line to the first node.
摘要翻译：电路包括第一节点，第二节点，存储器单元，第一数据线，第二数据线和写驱动器。存储器单元耦合到第一节点和第二节点，并由第一节点处的第一电压和第二节点处的第二电压供电。第一数据线和第二数据线耦合到存储器单元。写入驱动器具有在写入操作期间承载小于第一电压的第三电压的第三节点。写引导器耦合到第一数据线和第二数据线，并且被配置为在写操作期间，选择性地将第一数据线和第二数据线之一耦合到第三节点，并将第一数据中的另一个耦合线和第二条数据线到第一个节点。

9. 发明授权

US08391097B2 Memory word-line driver having reduced power consumption 有权
标题翻译：存储器字线驱动器具有降低的功耗
公开(公告)号：US08391097B2
公开(公告)日：2013-03-05
申请号：US12786791
申请日：2010-05-25
申请人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
发明人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C16/30 , G11C8/08
摘要： A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.
摘要翻译：用于驱动存储器阵列中的字线的字线驱动电路包括具有一对地址输入和输出的NAND电路，具有反相器电源节点的输出反相器电路，耦合到NAND的输出的输入电路和用于提供字线信号的输出，耦合在第一电源节点和逆变器电源节点之间的电源栅极以及耦合到电源门的控制电路。控制电路控制电源门以响应于NAND电路的输出将字线驱动电路置于有效或待机模式。

10. 发明申请

US20110292754A1 MEMORY WORD-LINE DRIVER HAVING REDUCED POWER CONSUMPTION 有权
标题翻译：具有降低功耗的存储器字线驱动器
公开(公告)号：US20110292754A1
公开(公告)日：2011-12-01
申请号：US12786791
申请日：2010-05-25
申请人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
发明人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
IPC分类号： G11C8/08
CPC分类号： G11C16/30 , G11C8/08
摘要： A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.
摘要翻译：用于驱动存储器阵列中的字线的字线驱动电路包括具有一对地址输入和输出的NAND电路，具有反相器电源节点的输出反相器电路，耦合到NAND的输出的输入电路和用于提供字线信号的输出，耦合在第一电源节点和逆变器电源节点之间的电源栅极以及耦合到电源门的控制电路。控制电路控制电源门以响应于NAND电路的输出将字线驱动电路置于有效或待机模式。

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