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1. 发明申请

US20100276761A1 Non-Planar Transistors and Methods of Fabrication Thereof 有权
标题翻译：非平面晶体管及其制造方法
公开(公告)号：US20100276761A1
公开(公告)日：2010-11-04
申请号：US12652947
申请日：2010-01-06
申请人： Chih-Hang Tung , Chin-Hsiang Lin , Cheng-Hung Chang , Sey-Ping Sun
发明人： Chih-Hang Tung , Chin-Hsiang Lin , Cheng-Hung Chang , Sey-Ping Sun
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7856 , H01L29/41791 , H01L29/66803 , H01L29/7839 , H01L29/785 , H01L2029/7858
摘要： Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.
摘要翻译：描述了非平面晶体管及其制造方法。在一个实施例中，形成非平面晶体管的方法包括在半导体鳍片的第一部分上形成沟道区域，所述半导体鳍片具有顶表面和侧壁。在半导体鳍片的沟道区域上形成栅电极，并且使用选择性外延生长工艺在栅电极的相对侧的半导体翅片的顶表面和侧壁上生长原位掺杂半导体层。掺杂半导体层的至少一部分被转换以形成掺杂剂浓度区域。

2. 发明授权

US09054194B2 Non-planar transistors and methods of fabrication thereof 有权
标题翻译：非平面晶体管及其制造方法
公开(公告)号：US09054194B2
公开(公告)日：2015-06-09
申请号：US12652947
申请日：2010-01-06
申请人： Chih-Hang Tung , Chin-Hsiang Lin , Cheng-Hung Chang , Sey-Ping Sun
发明人： Chih-Hang Tung , Chin-Hsiang Lin , Cheng-Hung Chang , Sey-Ping Sun
IPC分类号： H01L21/336 , H01L29/78 , H01L29/417 , H01L29/66
CPC分类号： H01L29/7856 , H01L29/41791 , H01L29/66803 , H01L29/7839 , H01L29/785 , H01L2029/7858
摘要： Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.
摘要翻译：描述了非平面晶体管及其制造方法。在一个实施例中，形成非平面晶体管的方法包括在半导体鳍片的第一部分上形成沟道区域，所述半导体鳍片具有顶表面和侧壁。在半导体鳍片的沟道区域上形成栅电极，并且使用选择性外延生长工艺在栅电极的相对侧的半导体翅片的顶表面和侧壁上生长原位掺杂半导体层。掺杂半导体层的至少一部分被转换以形成掺杂剂浓度区域。

3. 发明授权

US08946828B2 Semiconductor device having elevated structure and method of manufacturing the same 有权
标题翻译：具有升高的结构的半导体器件及其制造方法
公开(公告)号：US08946828B2
公开(公告)日：2015-02-03
申请号：US12702683
申请日：2010-02-09
申请人： Sey-Ping Sun , Tsung-Lin Lee , Chin-Hsiang Lin , Chih-Hao Chang , Chen-Nan Yeh , Chao-An Jong
发明人： Sey-Ping Sun , Tsung-Lin Lee , Chin-Hsiang Lin , Chih-Hao Chang , Chen-Nan Yeh , Chao-An Jong
IPC分类号： H01L29/78 , H01L21/768 , H01L29/66
CPC分类号： H01L29/4232 , H01L21/76834 , H01L21/76849 , H01L21/76897 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack.
摘要翻译：半导体器件包括半导体衬底; 覆盖衬底的栅极堆叠，形成在栅极堆叠的侧壁上的间隔物，以及覆盖栅极堆叠的保护层，用于填充由间隔物和栅极堆叠的顶表面围绕的空间的至少一部分。间隔件的顶表面高于栅极堆叠的顶表面。

4. 发明申请

US20110193144A1 SEMICONDUCTOR DEVICE HAVING ELEVATED STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有高度结构的半导体器件及其制造方法
公开(公告)号：US20110193144A1
公开(公告)日：2011-08-11
申请号：US12702683
申请日：2010-02-09
申请人： Sey-Ping Sun , Tsung-Lin Lee , Chin-Hsiang Lin , Chih-Hao Chang , Chen-Nan Yeh , Chao-An Jong
发明人： Sey-Ping Sun , Tsung-Lin Lee , Chin-Hsiang Lin , Chih-Hao Chang , Chen-Nan Yeh , Chao-An Jong
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/4232 , H01L21/76834 , H01L21/76849 , H01L21/76897 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack.
摘要翻译：半导体器件包括半导体衬底; 覆盖衬底的栅极堆叠，形成在栅极堆叠的侧壁上的间隔物，以及覆盖栅极堆叠的保护层，用于填充由间隔物和栅极堆叠的顶表面围绕的空间的至少一部分。间隔件的顶表面高于栅极堆叠的顶表面。

5. 发明授权

US08507996B2 Block contact plugs for MOS devices 有权
标题翻译：块接触器用于MOS器件
公开(公告)号：US08507996B2
公开(公告)日：2013-08-13
申请号：US12789046
申请日：2010-05-27
申请人： Sey-Ping Sun , Chih-Hao Chang , Chao-An Jong , Tsung-Lin Lee , Chung-Ju Lee , Chin-Hsiang Lin
发明人： Sey-Ping Sun , Chih-Hao Chang , Chao-An Jong , Tsung-Lin Lee , Chung-Ju Lee , Chin-Hsiang Lin
IPC分类号： H01L23/528
CPC分类号： H01L21/76897 , H01L21/76804 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate; a gate stack overlying the semiconductor substrate; a gate spacer on a sidewall of the gate stack; a first contact plug having an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack; and a second contact plug over and contacting the first contact plug. The second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact plug.
摘要翻译：集成电路结构包括半导体衬底; 覆盖半导体衬底的栅极堆叠; 在栅极堆叠的侧壁上的栅极间隔物; 具有接触所述栅极隔离物的侧壁的内边缘的第一接触插塞和具有所述栅极堆叠的顶表面的顶表面水平; 以及第二接触插头，并且与第一接触插塞接触。第二接触插塞的横截面积小于第一接触插塞的横截面面积。

6. 发明申请

US20110068411A1 Block Contact Plugs for MOS Devices 有权
标题翻译： MOS器件的块式触点插头
公开(公告)号：US20110068411A1
公开(公告)日：2011-03-24
申请号：US12789046
申请日：2010-05-27
申请人： Sey-Ping Sun , Chih-Hao Chang , Chao-An Jong , Tsung-Lin Lee , Chung-Ju Lee , Chin-Hsiang Lin
发明人： Sey-Ping Sun , Chih-Hao Chang , Chao-An Jong , Tsung-Lin Lee , Chung-Ju Lee , Chin-Hsiang Lin
IPC分类号： H01L29/78
CPC分类号： H01L21/76897 , H01L21/76804 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate; a gate stack overlying the semiconductor substrate; a gate spacer on a sidewall of the gate stack; a first contact plug having an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack; and a second contact plug over and contacting the first contact plug. The second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact plug.
摘要翻译：集成电路结构包括半导体衬底; 覆盖半导体衬底的栅极堆叠; 在栅极堆叠的侧壁上的栅极间隔物; 具有接触所述栅极隔离物的侧壁的内边缘的第一接触插塞和具有所述栅极堆叠的顶表面的顶表面水平; 以及第二接触插头，并且与第一接触插塞接触。第二接触插塞的横截面积小于第一接触插塞的横截面面积。

7. 发明授权

US08497556B2 Semiconductor devices with active semiconductor height variation 有权
标题翻译：具有半导体高度变化的半导体器件
公开(公告)号：US08497556B2
公开(公告)日：2013-07-30
申请号：US13607023
申请日：2012-09-07
申请人： David E. Brown , Hans Van Meer , Sey-Ping Sun
发明人： David E. Brown , Hans Van Meer , Sey-Ping Sun
IPC分类号： H01L31/119
CPC分类号： H01L29/0684 , H01L21/84 , H01L27/1203
摘要： A semiconductor product has different active thicknesses of silicon on a single semiconductor substrate. The thickness of the silicon layer is changed either by selectively adding silicon or subtracting silicon from an original layer of silicon. The different active thicknesses are suitable for use in different types of devices, such as diodes and transistors.
摘要翻译：半导体产品在单个半导体衬底上具有不同的有源厚度的硅。通过选择性地添加硅或从原始硅层减去硅来改变硅层的厚度。不同的有源厚度适用于不同类型的器件，例如二极管和晶体管。

8. 发明申请

US20130034948A1 Method of Manufacturing a Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130034948A1
公开(公告)日：2013-02-07
申请号：US13204352
申请日：2011-08-05
申请人： Gin-Chen Huang , Yi-An Lin , Ching-Hong Jiang , Neng-Kuo Chen , Sey-Ping Sun , Clement Hsingjen Wann
发明人： Gin-Chen Huang , Yi-An Lin , Ching-Hong Jiang , Neng-Kuo Chen , Sey-Ping Sun , Clement Hsingjen Wann
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/3081 , H01L21/31053 , H01L21/31055
摘要： A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.
摘要翻译：公开了一种制造半导体器件的方法。一种示例性方法包括提供衬底。在半导体衬底上形成电介质层，并在电介质层上形成阻挡层。阻挡层和电介质层包括不同的材料。该方法还包括在停止层上形成图案化的硬掩模层，并通过图案化的硬掩模层蚀刻半导体衬底以形成多个沟槽。该方法还包括在半导体衬底上沉积隔离材料并基本上填充多个沟槽。此后，在半导体衬底上执行CMP处理，其中CMP处理在停止层上停止。

9. 发明授权

US07053400B2 Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility 有权
标题翻译：基于具有高应力衬垫的Si-Ge的半导体器件，用于增强通道载流子迁移率
公开(公告)号：US07053400B2
公开(公告)日：2006-05-30
申请号：US10838330
申请日：2004-05-05
申请人： Sey-Ping Sun , David E. Brown
发明人： Sey-Ping Sun , David E. Brown
IPC分类号： H01L31/072
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823828 , H01L29/1054 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： The carrier mobility in transistor channel regions of Si—Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively or high tensilely stressed film, after post silicide spacer removal, over gate electrodes and strained Si source/drain regions of P-channel or N-channel transistors, respectively.
摘要翻译： Si-Ge器件的晶体管沟道区域中的载流子迁移率通过使用应力衬里而增加。实施例包括施加覆盖松弛的源极/漏极区域的高压缩或拉伸应力膜。其他实施例包括分别在栅极电极和P沟道或N沟道晶体管的应变Si源极/漏极区之后施加高度压缩或高拉伸应力膜，在硅化物间隔物去除之后。

10. 发明授权

US06265283B1 Self-aligning silicon oxynitride stack for improved isolation structure 有权
标题翻译：自对准硅氮氧化物叠层，用于改善隔离结构
公开(公告)号：US06265283B1
公开(公告)日：2001-07-24
申请号：US09373217
申请日：1999-08-12
申请人： Homi E. Nariman , Sey-Ping Sun , H. Jim Fulford
发明人： Homi E. Nariman , Sey-Ping Sun , H. Jim Fulford
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： Methods of fabricating an isolation structure on a substrate are provided. In one aspect, a method of fabricating an isolation structure on a substrate is provided that includes forming a first insulating layer on the substrate wherein the first insulating layer has a first sidewall. A trench is formed in the substrate that has a second sidewall. A second insulating layer is formed in the trench. The second insulating layer displaces the second sidewall laterally. The first insulating layer is densified by heating to liberate gas therefrom and thereby move the first sidewall into substantial vertical alignment with the second sidewall. The risk of substrate attack due to trench isolation structure pullback is reduced. Trench edges are covered by thick isolation material.
摘要翻译：提供了在基板上制造隔离结构的方法。一方面，提供一种在衬底上制造隔离结构的方法，包括在衬底上形成第一绝缘层，其中第一绝缘层具有第一侧壁。在具有第二侧壁的基板中形成沟槽。在沟槽中形成第二绝缘层。第二绝缘层横向移动第二侧壁。通过加热使第一绝缘层致密化，从而释放出气体，从而使第一侧壁与第二侧壁大致垂直对准。由于沟槽隔离结构回缩引起的基底侵蚀的风险降低。沟槽边缘被厚的隔离材料覆盖。

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