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1. 发明授权

US09159808B2 Selective etch-back process for semiconductor devices 有权
标题翻译：半导体器件的选择性回蚀工艺
公开(公告)号：US09159808B2
公开(公告)日：2015-10-13
申请号：US12617463
申请日：2009-11-12
申请人： Neng-Kuo Chen , Kuo-Hwa Tzeng , Cheng-Yuan Tsai
发明人： Neng-Kuo Chen , Kuo-Hwa Tzeng , Cheng-Yuan Tsai
IPC分类号： H01L21/311 , H01L29/66 , H01L21/762 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/31116 , H01L21/76232 , H01L29/7854
摘要： A semiconductor device having fins and a method of manufacture are provided. A patterned mask is formed over a substrate. Trenches are formed in the substrate and the trenches are filled with a dielectric material. Thereafter, the patterned mask is removed and one or more etch processes are performed to recess the dielectric material, wherein at least one of the etch processes is an etch process that removes or prevents fences from being formed along sidewalls of the trench. The etch process may be, for example, a plasma etch process using NH3 and NF3, an etch process using a polymer-rich gas, or an H2 etch process.
摘要翻译：提供了具有散热片和制造方法的半导体器件。在衬底上形成图案化掩模。在衬底中形成沟槽，并且沟槽填充有电介质材料。此后，去除图案化掩模并执行一个或多个蚀刻工艺以使电介质材料凹陷，其中至少一个蚀刻工艺是蚀刻工艺，该蚀刻工艺除去或防止围绕沟槽侧壁形成栅栏。蚀刻工艺可以是例如使用NH 3和NF 3的等离子体蚀刻工艺，使用富聚合气体的蚀刻工艺或H 2蚀刻工艺。

2. 发明授权

US08546242B2 Hybrid gap-fill approach for STI formation 有权
标题翻译：混合间隙填充方法用于STI形成
公开(公告)号：US08546242B2
公开(公告)日：2013-10-01
申请号：US13481526
申请日：2012-05-25
申请人： Neng-Kuo Chen , Chih-Hsiang Chang , Kuo-Hwa Tzeng , Cheng-Yuan Tsai
发明人： Neng-Kuo Chen , Chih-Hsiang Chang , Kuo-Hwa Tzeng , Cheng-Yuan Tsai
IPC分类号： H01L21/8238
CPC分类号： H01L21/76224
摘要： A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition method to fill a dielectric material into the opening; performing a first treatment on the dielectric material, wherein the first treatment provides an energy high enough for breaking bonds in the dielectric material; and performing a steam anneal on the dielectric material.
摘要翻译：提供了形成浅沟槽隔离区域的方法。该方法包括提供包括顶表面的半导体衬底; 形成从所述顶表面延伸到所述半导体衬底中的开口; 执行保形沉积方法以将电介质材料填充到开口中; 对所述电介质材料进行第一处理，其中所述第一处理提供足够高的能量以破坏所述电介质材料中的键; 并对介电材料进行蒸汽退火。

3. 发明申请

US20130043512A1 Semiconductor Device Manufacturing Methods and Methods of Forming Insulating Material Layers 有权
公开(公告)号：US20130043512A1
公开(公告)日：2013-02-21
申请号：US13212834
申请日：2011-08-18
申请人： Gin-Chen Huang , Tsai-Fu Hsiao , Ching-Hong Jiang , Neng-Kuo Chen , Hongfa Luan , Sey-Ping Sun , Clement Hsingjen Wann
发明人： Gin-Chen Huang , Tsai-Fu Hsiao , Ching-Hong Jiang , Neng-Kuo Chen , Hongfa Luan , Sey-Ping Sun , Clement Hsingjen Wann
IPC分类号： H01L21/31 , H01L21/28 , H01L29/78
CPC分类号： H01L21/02274 , H01L21/02164 , H01L21/022 , H01L21/0228 , H01L21/02332 , H01L21/324 , H01L29/66795
摘要： Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

4. 发明授权

US08367534B2 Non-uniformity reduction in semiconductor planarization 有权
标题翻译：半导体平面化不均匀性降低
公开(公告)号：US08367534B2
公开(公告)日：2013-02-05
申请号：US12884500
申请日：2010-09-17
申请人： Neng-Kuo Chen , Jeff J. Xu
发明人： Neng-Kuo Chen , Jeff J. Xu
IPC分类号： H01L21/20
CPC分类号： H01L21/02337 , H01L21/28123 , H01L21/31116 , H01L21/32115 , H01L21/32137
摘要： Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.
摘要翻译：提供了一种使半导体器件平坦化的方法。该方法包括提供基板。该方法包括在衬底上形成第一层。该方法包括在第一层上形成第二层。第一层和第二层具有不同的材料组成。该方法包括在第二层上形成第三层。该方法包括在第三层上进行抛光处理，直到第三层基本上被去除。该方法包括执行回蚀处理以去除第二层和第一层的一部分。其中相对于第一层和第二层的蚀刻返回工艺的蚀刻选择性为约1:1。

5. 发明申请

US20120235273A1 Hybrid Gap-fill Approach for STI Formation 有权
标题翻译：用于STI形成的混合间隙填充方法
公开(公告)号：US20120235273A1
公开(公告)日：2012-09-20
申请号：US13481526
申请日：2012-05-25
申请人： Neng-Kuo Chen , Chih-Hsiang Chang , Kuo-Hwa Tzeng , Cheng-Yuan Tsai
发明人： Neng-Kuo Chen , Chih-Hsiang Chang , Kuo-Hwa Tzeng , Cheng-Yuan Tsai
IPC分类号： H01L29/06
CPC分类号： H01L21/76224
摘要： A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition method to fill a dielectric material into the opening; performing a first treatment on the dielectric material, wherein the first treatment provides an energy high enough for breaking bonds in the dielectric material; and performing a steam anneal on the dielectric material.
摘要翻译：提供了形成浅沟槽隔离区域的方法。该方法包括提供包括顶表面的半导体衬底; 形成从所述顶表面延伸到所述半导体衬底中的开口; 执行保形沉积方法以将电介质材料填充到开口中; 对所述电介质材料进行第一处理，其中所述第一处理提供足够高的能量以破坏所述电介质材料中的键; 并对介电材料进行蒸汽退火。

6. 发明授权

US07846804B2 Method for fabricating high tensile stress film 有权
标题翻译：高拉伸应力薄膜的制造方法
公开(公告)号：US07846804B2
公开(公告)日：2010-12-07
申请号：US11758623
申请日：2007-06-05
申请人： Hsiu-Lien Liao , Neng-Kuo Chen , Teng-Chun Tsai , Yi-Wei Chen
发明人： Hsiu-Lien Liao , Neng-Kuo Chen , Teng-Chun Tsai , Yi-Wei Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L29/665 , H01L29/66575 , H01L29/78 , H01L29/7843
摘要： A method and an apparatus for fabricating a high tensile stress film includes providing a substrate, forming a poly stressor on the substrate, and performing an ultra violet rapid thermal process (UVRTP) for curing the poly stressor and adjusting its tensile stress status, thus the poly stressor serves as a high tensile stress film. Due to a combination of energy from photons and heat, the tensile stress status of the high tensile stress film is adjusted in a relatively shorter process period or under a relatively lower temperature.
摘要翻译：用于制造高拉伸应力膜的方法和装置包括提供基板，在基板上形成多应力器，并执行紫外线快速热处理（UVRTP），用于固化聚应力器并调整其拉伸应力状态，因此多应力器作为高拉伸应力膜。由于来自光子和热的能量的组合，高拉伸应力膜的拉伸应力状态在相对较短的工艺周期或相对较低的温度下调节。

7. 发明申请

US20100252794A1 COMPOSITE FILM FOR PHASE CHANGE MEMORY DEVICES 有权
标题翻译：用于相变存储器件的复合膜
公开(公告)号：US20100252794A1
公开(公告)日：2010-10-07
申请号：US12750323
申请日：2010-03-30
申请人： Tung-Ti YEH , Neng-Kuo CHEN , Cheng-Yuan TSAI , Chung-Yi YU , Chia-Shiung TSAI
发明人： Tung-Ti YEH , Neng-Kuo CHEN , Cheng-Yuan TSAI , Chung-Yi YU , Chia-Shiung TSAI
IPC分类号： H01L45/00 , H01L21/06
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/144 , H01L45/1675
摘要： A phase change memory device and a method of manufacture are provided. The phase change memory device includes a phase change layer electrically coupled to a top electrode and a bottom electrode, the phase change layer comprising a phase change material. A mask layer is formed overlying the phase change layer. A first sealing layer is formed overlying the mask layer, and a second sealing layer is formed overlying the first sealing layer.
摘要翻译：提供了一种相变存储器件及其制造方法。相变存储器件包括电耦合到顶电极和底电极的相变层，所述相变层包括相变材料。掩模层形成在相变层上。形成覆盖在掩模层上的第一密封层，并且形成覆盖在第一密封层上的第二密封层。

8. 发明申请

US20100213431A1 Treated Chalcogenide Layer for Semiconductor Devices 审中-公开
标题翻译：处理半导体器件的硫族化物层
公开(公告)号：US20100213431A1
公开(公告)日：2010-08-26
申请号：US12617294
申请日：2009-11-12
申请人： Tung-Ti Yeh , Chih-Ming Chen , Chung-Yi Yu , Cheng-Yuan Tsai , Neng-Kuo Chen , Chia-Shiung Tsai
发明人： Tung-Ti Yeh , Chih-Ming Chen , Chung-Yi Yu , Cheng-Yuan Tsai , Neng-Kuo Chen , Chia-Shiung Tsai
IPC分类号： H01L29/24 , H01L21/10
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/144 , H01L45/1641 , H01L45/1675
摘要： A phase change memory and a method of manufacture are provided. The phase change memory includes a layer of phase change material treated to increase the hydrophobic nature of the phase change material. The hydrophobic nature of the phase change material improves adhesion between the phase change material and an overlying mask layer. The phase change material may be treated, for example, with a plasma comprising N2, NH3, Ar, He, O2, H2, or the like.
摘要翻译：提供了相变存储器和制造方法。相变存储器包括被处理以增加相变材料的疏水性质的相变材料层。相变材料的疏水性改善了相变材料与上覆掩模层之间的粘合性。相变材料可以例如用包含N 2，NH 3，Ar，He，O 2，H 2等的等离子体处理。

9. 发明申请

US20090280614A1 Method of making a P-type metal-oxide semiconductor transistor and method of making a complementary metal-oxide semiconductor transistor 审中-公开
标题翻译：制造P型金属氧化物半导体晶体管的方法和制造互补金属氧化物半导体晶体管的方法
公开(公告)号：US20090280614A1
公开(公告)日：2009-11-12
申请号：US12503042
申请日：2009-07-14
申请人： Neng-Kuo Chen , Chien-Chung Huang , Jei-Ming Chen
发明人： Neng-Kuo Chen , Chien-Chung Huang , Jei-Ming Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L21/2658 , H01L21/823807 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method is disclosed to make a strained-silicon PMOS or CMOS transistor, in which, a compressive stress film is formed by reacting a silane having at least one substituent selected from the group consisting of hydrocarbyl, hydrocarboxy, carbonyl, formyl, carboxylic group, ester group, and halo group and ammonia, or a conventional compressive stress film is implanted with fluorine atoms, oxygen atoms, or carbon atoms, so as to improve the properties of negative bias temperature instability (NBTI).
摘要翻译：公开了制造应变硅PMOS或CMOS晶体管的方法，其中通过使具有至少一个选自烃基，烃羧基，羰基，甲酰基，羧基的取代基的硅烷反应形成压应力膜，酯基，卤代基和氨，或者常规的压应力膜注入氟原子，氧原子或碳原子，以提高负偏压温度不稳定性（NBTI）的性质。

10. 发明申请

US20090274852A1 METHOD FOR FABRICATING HIGH COMPRESSIVE STRESS FILM AND STRAINED-SILICON TRANSISTORS 审中-公开
标题翻译：用于制造高压应力膜和应变硅晶体管的方法
公开(公告)号：US20090274852A1
公开(公告)日：2009-11-05
申请号：US12496652
申请日：2009-07-02
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang
IPC分类号： B05D1/00
CPC分类号： H01L21/31633 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/823807 , H01L23/3192 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating strained silicon transistors is disclosed. First, a semiconductor substrate is provided, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region formed thereon. Next, a precursor, silane, and ammonia are injected, in which the precursor is reacted with silane and ammonia to form a high compressive stress film on the surface of the gate, the spacer, and the source/drain region. Preferably, the high compressive stress film can be utilized in the fabrication of a poly stressor, a contact etch stop layer, and dual contact etch stop layers.
摘要翻译：公开了制造应变硅晶体管的方法。首先，提供半导体衬底，其中半导体衬底包括栅极，至少一个间隔物和形成在其上的源极/漏极区域。接下来，注入前体，硅烷和氨，其中前体与硅烷和氨反应，以在栅极，间隔物和源极/漏极区的表面上形成高压缩应力膜。优选地，高压缩应力膜可以用于制造多应力器，接触蚀刻停止层和双接触蚀刻停止层。

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