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1. 发明授权

US06841441B2 Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing 有权
标题翻译：用于使用溅射金属沉积，金属离子注入或硅注入的CMOS器件和激光退火的双栅极（一个金属和一个多晶硅或金属硅化物）的制造方法
公开(公告)号：US06841441B2
公开(公告)日：2005-01-11
申请号：US10338156
申请日：2003-01-08
申请人： Chew Hoe Ang , Eng-Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
发明人： Chew Hoe Ang , Eng-Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： H01L21/268 , H01L21/28 , H01L21/8238 , H01L29/49
CPC分类号： H01L29/4933 , H01L21/268 , H01L21/28061 , H01L21/823842
摘要： A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.
摘要翻译：一种制造第一和第二栅极的方法，包括以下步骤。提供了其上形成有栅介电层的基板。衬底具有第一栅极区域和第二栅极区域。在栅极电介质层上形成薄的第一栅极层。第二栅极区域内的薄的第一栅极层被掩蔽以暴露第一栅极区域内的薄的第一栅极层的一部分。薄的第一栅极层的暴露部分被转换成薄的第三栅极层部分。在薄的第一和第三栅极层部分上形成第二栅极层。第二栅极层和第一和第三栅极层部分被图案化以在第一栅极区域内形成第一栅极，在第二栅极区域内形成第二栅极。

2. 发明授权

US06664153B2 Method to fabricate a single gate with dual work-functions 失效
标题翻译：制造具有双功能功能的单门的方法
公开(公告)号：US06664153B2
公开(公告)日：2003-12-16
申请号：US10072099
申请日：2002-02-08
申请人： Chew Hoe Ang , Eng Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
发明人： Chew Hoe Ang , Eng Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
IPC分类号： H01L21336
CPC分类号： H01L29/4983 , H01L21/28035
摘要： A method for forming a single gate having a dual work-function is described. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-function and whereby a central portion of the gate electrode not doped has a second work-function to complete formation of a single gate having multiple work-functions in the fabrication of integrated circuits.
摘要翻译：描述了一种形成具有双功能功能的单门的方法。在基板上形成覆盖栅介质层的栅电极。栅电极的侧壁被选择性掺杂，由此掺杂侧壁具有第一功函数，并且由此未掺杂的栅电极的中心部分具有第二功函数，以在制造中完成形成具有多个功函数的单个栅极的集成电路。

3. 发明授权

US06429109B1 Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate 有权
标题翻译：通过在氧化物和栅极之间使用牺牲金属来形成高k电介质和硅化物以减少多余的方法
公开(公告)号：US06429109B1
公开(公告)日：2002-08-06
申请号：US10017953
申请日：2001-12-14
申请人： Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen , Chew Hoe Ang , Eng Hua Lim , Randall Cha
发明人： Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen , Chew Hoe Ang , Eng Hua Lim , Randall Cha
IPC分类号： H01L214763
CPC分类号： H01L21/28194 , H01L21/28097 , H01L21/28176 , H01L21/28238 , H01L29/513 , H01L29/517
摘要： A method of forming a gate comprising the following steps. A substrate is provided. A pre-gate structure is formed over the substrate. The pregate structure includes a sacrificial metal layer between an upper gate conductor layer and a lower gate dielectric layer. The pre-gate structure is annealed to form the gate. The gate comprising: an upper silicide layer formed from a portion of the sacrificial metal layer and a portion of the upper gate conductor layer from the anneal; and a lower metal oxide layer formed from a portion of the gate dielectric layer and a portion of the sacrificial metal layer from the anneal.
摘要翻译：一种形成浇口的方法，包括以下步骤。提供基板。在衬底上形成预栅极结构。预栅结构包括在上栅极导体层和下栅极介电层之间的牺牲金属层。预栅结构退火形成栅极。该栅极包括：由牺牲金属层的一部分形成的上硅化物层和来自退火的上部栅极导体层的一部分; 以及由栅极电介质层的一部分和来自退火的牺牲金属层的一部分形成的下部金属氧化物层。

4. 发明授权

US06632712B1 Method of fabricating variable length vertical transistors 失效
标题翻译：制造可变长度垂直晶体管的方法
公开(公告)号：US06632712B1
公开(公告)日：2003-10-14
申请号：US10263895
申请日：2002-10-03
申请人： Chew-Hoe Ang , Eng Hua Lim , Randall Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
发明人： Chew-Hoe Ang , Eng Hua Lim , Randall Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
IPC分类号： H01L218238
CPC分类号： H01L29/66666 , H01L21/823885 , H01L29/7827
摘要： A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the composite insulator stack. Selective removal of specific components of the composite insulator stack, in a specific region, allows the depth of the channel openings to be varied. A subsequent epitaxial silicon growth procedure fills the variable depth channel openings, providing the variable length, channel regions for the vertical CMOS devices.
摘要翻译：已经开发了用于制造具有可变通道长度的垂直CMOS器件的工艺。通道区域开口限定在复合绝缘体堆叠中，特定器件的通道长度由复合绝缘子堆叠的厚度确定。在特定区域中选择性去除复合绝缘子堆叠的特定部件允许沟道开口的深度变化。随后的外延硅生长过程填充可变深度通道开口，为垂直CMOS器件提供可变长度的沟道区。

5. 发明授权

US06544848B1 Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers 失效
标题翻译：使用小的原位掺杂多晶硅间隔物形成非对称非易失性存储器件的方法
公开(公告)号：US06544848B1
公开(公告)日：2003-04-08
申请号：US10224212
申请日：2002-08-20
申请人： Chew Hoe Ang , Eng Hua Lim , Randall Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
发明人： Chew Hoe Ang , Eng Hua Lim , Randall Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , H01L21/28273
摘要： A new method of forming a sharp tip on a floating gate in the fabrication of a EEPROM memory cell is described. A first gate dielectric layer is provided on a substrate. A second gate dielectric layer is deposited overlying the first gate dielectric layer. A floating gate/control gate stack is formed overlying the second gate dielectric layer. One sidewall portion of the floating gate is covered with a mask. The second gate dielectric layer not covered by the mask is etched away whereby an undercut of the floating gate is formed in the second gate dielectric layer. The mask is removed. Polysilicon spacers are formed on sidewalls of the floating gate wherein one of the polysilicon spacers fills the undercut thereby forming a sharp polysilicon tip to improve the erase efficiency of the memory cell.
摘要翻译：描述了在EEPROM存储器单元的制造中在浮动栅极上形成尖端尖端的新方法。第一栅介质层设置在基板上。第二栅介质层沉积在第一栅介质层上。形成覆盖在第二栅极电介质层上的浮栅/控制栅叠层。浮动栅极的一个侧壁部分被掩模覆盖。被掩模未被覆盖的第二栅极电介质层被蚀刻掉，从而在第二栅极介质层中形成浮栅的底切。去除面具。多晶硅间隔物形成在浮置栅极的侧壁上，其中多晶硅间隔物中的一个填充底切，从而形成尖锐的多晶硅尖端，以提高存储单元的擦除效率。

6. 发明授权

US06664156B1 Method for forming L-shaped spacers with precise width control 有权
标题翻译：用于形成具有精确宽度控制的L形间隔件的方法
公开(公告)号：US06664156B1
公开(公告)日：2003-12-16
申请号：US10209573
申请日：2002-07-31
申请人： Chew Hoe Ang , Eng Hua Lim , Wenhe Lin , Jia Zhen Zheng
发明人： Chew Hoe Ang , Eng Hua Lim , Wenhe Lin , Jia Zhen Zheng
IPC分类号： H01L21311
CPC分类号： H01L29/6653 , H01L29/4983 , H01L29/6656 , H01L29/6659
摘要： A method of fabrication of L-shaped spacers in a semiconductor device. A gate structure is provided over a substrate. We form a first dielectric layer over the gate dielectric layer and the substrate. Next, a second dielectric layer is formed over the first dielectric layer. Then, we form a third dielectric layer over the second dielectric layer. The third dielectric layer is anisotropically etched to form a disposable spacer on the second dielectric layer. The second dielectric layer and the first dielectric layer are anisotropically etched using the disposable spacer as a mask to form a top and a bottom L-shaped spacer. The disposable spacer is removed. In preferred embodiments, the first, second and third dielectric layers are formed by atomic layer deposition (ALD) or ALCVD processes.
摘要翻译：一种在半导体器件中制造L形间隔物的方法。栅极结构设置在衬底上。我们在栅极电介质层和衬底上形成第一电介质层。接下来，在第一电介质层上形成第二电介质层。然后，在第二电介质层上形成第三电介质层。第三介电层被各向异性蚀刻以在第二介电层上形成一次性间隔物。使用一次性间隔件作为掩模对第二介电层和第一介电层进行各向异性蚀刻，以形成顶部和底部的L形间隔件。去除一次性间隔物。在优选实施例中，第一，第二和第三电介质层通过原子层沉积（ALD）或ALCVD工艺形成。

7. 发明授权

US06762085B2 Method of forming a high performance and low cost CMOS device 有权
标题翻译：形成高性能和低成本CMOS器件的方法
公开(公告)号：US06762085B2
公开(公告)日：2004-07-13
申请号：US10262169
申请日：2002-10-01
申请人： Jia Zhen Zheng , Soh Yun Siah , Liang Choo Hsia , Eng Hua Lim , Simon Chooi , Chew Hoe Ang
发明人： Jia Zhen Zheng , Soh Yun Siah , Liang Choo Hsia , Eng Hua Lim , Simon Chooi , Chew Hoe Ang
IPC分类号： H01L218238
CPC分类号： H01L29/66598 , H01L21/823814 , H01L21/823835 , H01L21/823864
摘要： A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped silicon oxide spacers on the sides of gate structures, with a vertical spacer component located on the sides of the gate structure, and with horizontal spacer components located on the surface of the semiconductor substrate with a thick horizontal spacer component located adjacent to the gate structures, while a thinner horizontal spacer component is located adjacent to the thicker horizontal spacer component. After formation of a block out shape in a PMOS region of the CMOS device, a high angle implantation procedure is used to form a P type halo region in a top portion of the NMOS region, followed by another implantation procedure performed at lower implant angles, resulting in an N type LDD region in a portion of the NMOS region underlying the thicker horizontal spacer component, and resulting in an N type heavily doped source/drain region in a portion of the NMOS underlying the thinner horizontal spacer component. Another block out shape, and another series of similar implantation procedures is performed to create the halo, LDD and source/drain regions in the PMOS region. After formation of a photoresist block out shape on specific CMOS regions, a composite insulator spacer is formed on the sides of gate structures not covered by the photoresist shape, followed by formation of metal silicide on the gate structures and source/drain regions not covered by the photoresist block out shape.
摘要翻译：已经开发了由于光刻掩模程序的减少而制造具有降低的处理成本的CMOS器件的方法。该方法特征是在栅极结构的侧面上形成L形氧化硅间隔物，其中垂直间隔件部件位于栅极结构的侧面，并且水平间隔件部件位于半导体衬底的表面上，具有厚的水平间隔件位于邻近门结构的位置，而较薄的水平间隔件组件位于较厚的水平间隔件部件附近。在CMOS器件的PMOS区域中形成块状形状之后，使用高角度注入工艺在NMOS区域的顶部形成P型卤素区域，随后以较低的注入角度进行另一种注入工艺，导致在较厚的水平间隔器部件下面的NMOS区域的一部分中的N型LDD区域，并且导致在较薄的水平间隔器部件下面的NMOS的一部分中的N型重掺杂的源极/漏极区域。执行另一个块状形状，并且进行另一系列相似的注入工艺以在PMOS区域中产生卤素，LDD和源极/漏极区域。在特定CMOS区域上形成光致抗蚀剂阻挡形状之后，在未被光致抗蚀剂形状覆盖的栅极结构的侧面上形成复合绝缘体间隔物，然后在栅极结构和未被覆盖的源极/漏极区域上形成金属硅化物光致抗蚀剂阻挡形状。

8. 发明授权

US06780691B2 Method to fabricate elevated source/drain transistor with large area for silicidation 失效
公开(公告)号：US06780691B2
公开(公告)日：2004-08-24
申请号：US10222410
申请日：2002-08-16
申请人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex Kai Hung See , Jia Zhen Zheng
发明人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex Kai Hung See , Jia Zhen Zheng
IPC分类号： H01L2100
CPC分类号： H01L29/66583 , H01L21/28123 , H01L21/76235 , H01L21/823814 , H01L29/41783 , H01L29/665
摘要： A method for forming a transistor having an elevated source/drain structure is described. A gate electrode is formed overlying a substrate and isolated from the substrate by a gate dielectric layer. Isolation regions are formed in and on the substrate wherein the isolation regions have a stepped profile wherein an upper portion of the isolation regions partly overlaps and is offset from a lower portion of the isolation regions in the direction away from the gate electrode. Ions are implanted into the substrate between the gate electrode and the isolation regions to form source/drain extensions. Dielectric spacers are formed on sidewalls of the gate electrode and the isolation regions. A conductive layer is deposited overlying the substrate, the gate electrode, and the isolation regions and planarized to leave the conductive layer adjacent to the gate electrode and separated from the gate electrode by the dielectric spacers wherein the conductive layer forms elevated source/drain junctions and wherein the elevated source/drain junctions completely overlie the source/drain extensions and wherein an upper portion of the elevated source/drain junctions extends into the stepped portion of the isolation regions thereby completing formation of a MOSFET having an elevated source/drain structure.

9. 发明授权

US06830971B2 High K artificial lattices for capacitor applications to use in CU or AL BEOL 有权
标题翻译：用于电容器应用的高K人造晶格用于CU或AL BEOL
公开(公告)号：US06830971B2
公开(公告)日：2004-12-14
申请号：US10286627
申请日：2002-11-02
申请人： Subramanian Balakumar , Chew Hoe Ang , Jia Zhen Zheng , Paul Proctor
发明人： Subramanian Balakumar , Chew Hoe Ang , Jia Zhen Zheng , Paul Proctor
IPC分类号： H01L218242
CPC分类号： H01L28/56 , H01L21/3141 , H01L21/3142 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L28/90
摘要： A process of fabricating high dielectric constant MIM capacitors. The high dielectric constant MIM capacitors are for both RF and analog circuit applications. For the high dielectric constant MIM capacitors, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of artificial layers. Dielectric constants near 900 can be achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques are employed for the layer growth processes.
摘要翻译：制造高介电常数MIM电容器的工艺。高介电常数MIM电容器适用于RF和模拟电路应用。对于高介电常数MIM电容器，金属由双重镶嵌工艺中的铜电极组成。超级晶格的介电常数与总厚度的关系由人造层的数量来控制。接近900的介电常数可以达到250埃厚的超晶格。 MBE，分子束外延或ALCVD，原子层CVD技术用于层生长过程。

10. 发明授权

US06586314B1 Method of forming shallow trench isolation regions with improved corner rounding 失效
标题翻译：形成浅沟槽隔离区域的方法具有改进的拐角圆角
公开(公告)号：US06586314B1
公开(公告)日：2003-07-01
申请号：US10266952
申请日：2002-10-08
申请人： Soh Yun Siah , Liang Choo Hsia , Jia Zhen Zheng , Chew Hoe Ang
发明人： Soh Yun Siah , Liang Choo Hsia , Jia Zhen Zheng , Chew Hoe Ang
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A method of forming a shallow trench isolation (STI), region in a semiconductor substrate featuring a process sequence that results in desired rounded corners for the sides of active device regions located butting the STI region, has been developed. The process sequence features formation of, followed by removal of, a silicon dioxide layer which was thermally grown in a top portion of the semiconductor substrate, wherein the top portion of semiconductor was subjected to an ion implantation procedure prior to the oxidation procedure. The above process sequence results in a recessed portion of semiconductor located adjacent to unoxidized portions of semiconductor which underlay an oxidation resistant shape, and feature rounded corners. Insulator spacers are then formed on the sides of the oxidation resistant shape, overlying and protecting the rounded comers of subsequent active device regions from a dry etch procedure used to selectively define a shallow trench shape in the exposed semiconductor region. Insulator filling and planarization procedures result in the formation of an STI region, located adjacent to active device regions which feature the desired rounded corners.
摘要翻译：已经开发了在半导体衬底中形成浅沟槽隔离（STI）区域的方法，该半导体衬底的特征在于产生针对STI区域的有源器件区域的侧面的期望的圆角的工艺序列。处理顺序特征在于形成，随后除去在半导体衬底的顶部热生长的二氧化硅层，其中半导体的顶部在氧化过程之前进行离子注入工艺。上述处理顺序导致位于半导体的未氧化部分附近的半导体的凹陷部分，其具有抗氧化的形状，并且具有圆角。然后在耐氧化形状的侧面上形成绝缘体间隔物，覆盖并保护随后的有源器件区域的圆角从用于在暴露的半导体区域中选择性地限定浅沟槽形状的干蚀刻工艺。绝缘体填充和平坦化程序导致STI区域的形成，其位于具有所需圆角的有源器件区域附近。

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