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1. 发明授权

US06762085B2 Method of forming a high performance and low cost CMOS device 有权
标题翻译：形成高性能和低成本CMOS器件的方法
公开(公告)号：US06762085B2
公开(公告)日：2004-07-13
申请号：US10262169
申请日：2002-10-01
申请人： Jia Zhen Zheng , Soh Yun Siah , Liang Choo Hsia , Eng Hua Lim , Simon Chooi , Chew Hoe Ang
发明人： Jia Zhen Zheng , Soh Yun Siah , Liang Choo Hsia , Eng Hua Lim , Simon Chooi , Chew Hoe Ang
IPC分类号： H01L218238
CPC分类号： H01L29/66598 , H01L21/823814 , H01L21/823835 , H01L21/823864
摘要： A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped silicon oxide spacers on the sides of gate structures, with a vertical spacer component located on the sides of the gate structure, and with horizontal spacer components located on the surface of the semiconductor substrate with a thick horizontal spacer component located adjacent to the gate structures, while a thinner horizontal spacer component is located adjacent to the thicker horizontal spacer component. After formation of a block out shape in a PMOS region of the CMOS device, a high angle implantation procedure is used to form a P type halo region in a top portion of the NMOS region, followed by another implantation procedure performed at lower implant angles, resulting in an N type LDD region in a portion of the NMOS region underlying the thicker horizontal spacer component, and resulting in an N type heavily doped source/drain region in a portion of the NMOS underlying the thinner horizontal spacer component. Another block out shape, and another series of similar implantation procedures is performed to create the halo, LDD and source/drain regions in the PMOS region. After formation of a photoresist block out shape on specific CMOS regions, a composite insulator spacer is formed on the sides of gate structures not covered by the photoresist shape, followed by formation of metal silicide on the gate structures and source/drain regions not covered by the photoresist block out shape.
摘要翻译：已经开发了由于光刻掩模程序的减少而制造具有降低的处理成本的CMOS器件的方法。该方法特征是在栅极结构的侧面上形成L形氧化硅间隔物，其中垂直间隔件部件位于栅极结构的侧面，并且水平间隔件部件位于半导体衬底的表面上，具有厚的水平间隔件位于邻近门结构的位置，而较薄的水平间隔件组件位于较厚的水平间隔件部件附近。在CMOS器件的PMOS区域中形成块状形状之后，使用高角度注入工艺在NMOS区域的顶部形成P型卤素区域，随后以较低的注入角度进行另一种注入工艺，导致在较厚的水平间隔器部件下面的NMOS区域的一部分中的N型LDD区域，并且导致在较薄的水平间隔器部件下面的NMOS的一部分中的N型重掺杂的源极/漏极区域。执行另一个块状形状，并且进行另一系列相似的注入工艺以在PMOS区域中产生卤素，LDD和源极/漏极区域。在特定CMOS区域上形成光致抗蚀剂阻挡形状之后，在未被光致抗蚀剂形状覆盖的栅极结构的侧面上形成复合绝缘体间隔物，然后在栅极结构和未被覆盖的源极/漏极区域上形成金属硅化物光致抗蚀剂阻挡形状。

2. 发明授权

US06664156B1 Method for forming L-shaped spacers with precise width control 有权
标题翻译：用于形成具有精确宽度控制的L形间隔件的方法
公开(公告)号：US06664156B1
公开(公告)日：2003-12-16
申请号：US10209573
申请日：2002-07-31
申请人： Chew Hoe Ang , Eng Hua Lim , Wenhe Lin , Jia Zhen Zheng
发明人： Chew Hoe Ang , Eng Hua Lim , Wenhe Lin , Jia Zhen Zheng
IPC分类号： H01L21311
CPC分类号： H01L29/6653 , H01L29/4983 , H01L29/6656 , H01L29/6659
摘要： A method of fabrication of L-shaped spacers in a semiconductor device. A gate structure is provided over a substrate. We form a first dielectric layer over the gate dielectric layer and the substrate. Next, a second dielectric layer is formed over the first dielectric layer. Then, we form a third dielectric layer over the second dielectric layer. The third dielectric layer is anisotropically etched to form a disposable spacer on the second dielectric layer. The second dielectric layer and the first dielectric layer are anisotropically etched using the disposable spacer as a mask to form a top and a bottom L-shaped spacer. The disposable spacer is removed. In preferred embodiments, the first, second and third dielectric layers are formed by atomic layer deposition (ALD) or ALCVD processes.
摘要翻译：一种在半导体器件中制造L形间隔物的方法。栅极结构设置在衬底上。我们在栅极电介质层和衬底上形成第一电介质层。接下来，在第一电介质层上形成第二电介质层。然后，在第二电介质层上形成第三电介质层。第三介电层被各向异性蚀刻以在第二介电层上形成一次性间隔物。使用一次性间隔件作为掩模对第二介电层和第一介电层进行各向异性蚀刻，以形成顶部和底部的L形间隔件。去除一次性间隔物。在优选实施例中，第一，第二和第三电介质层通过原子层沉积（ALD）或ALCVD工艺形成。

3. 发明授权

US06632712B1 Method of fabricating variable length vertical transistors 失效
标题翻译：制造可变长度垂直晶体管的方法
公开(公告)号：US06632712B1
公开(公告)日：2003-10-14
申请号：US10263895
申请日：2002-10-03
申请人： Chew-Hoe Ang , Eng Hua Lim , Randall Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
发明人： Chew-Hoe Ang , Eng Hua Lim , Randall Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
IPC分类号： H01L218238
CPC分类号： H01L29/66666 , H01L21/823885 , H01L29/7827
摘要： A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the composite insulator stack. Selective removal of specific components of the composite insulator stack, in a specific region, allows the depth of the channel openings to be varied. A subsequent epitaxial silicon growth procedure fills the variable depth channel openings, providing the variable length, channel regions for the vertical CMOS devices.
摘要翻译：已经开发了用于制造具有可变通道长度的垂直CMOS器件的工艺。通道区域开口限定在复合绝缘体堆叠中，特定器件的通道长度由复合绝缘子堆叠的厚度确定。在特定区域中选择性去除复合绝缘子堆叠的特定部件允许沟道开口的深度变化。随后的外延硅生长过程填充可变深度通道开口，为垂直CMOS器件提供可变长度的沟道区。

4. 发明授权

US06544848B1 Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers 失效
标题翻译：使用小的原位掺杂多晶硅间隔物形成非对称非易失性存储器件的方法
公开(公告)号：US06544848B1
公开(公告)日：2003-04-08
申请号：US10224212
申请日：2002-08-20
申请人： Chew Hoe Ang , Eng Hua Lim , Randall Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
发明人： Chew Hoe Ang , Eng Hua Lim , Randall Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , H01L21/28273
摘要： A new method of forming a sharp tip on a floating gate in the fabrication of a EEPROM memory cell is described. A first gate dielectric layer is provided on a substrate. A second gate dielectric layer is deposited overlying the first gate dielectric layer. A floating gate/control gate stack is formed overlying the second gate dielectric layer. One sidewall portion of the floating gate is covered with a mask. The second gate dielectric layer not covered by the mask is etched away whereby an undercut of the floating gate is formed in the second gate dielectric layer. The mask is removed. Polysilicon spacers are formed on sidewalls of the floating gate wherein one of the polysilicon spacers fills the undercut thereby forming a sharp polysilicon tip to improve the erase efficiency of the memory cell.
摘要翻译：描述了在EEPROM存储器单元的制造中在浮动栅极上形成尖端尖端的新方法。第一栅介质层设置在基板上。第二栅介质层沉积在第一栅介质层上。形成覆盖在第二栅极电介质层上的浮栅/控制栅叠层。浮动栅极的一个侧壁部分被掩模覆盖。被掩模未被覆盖的第二栅极电介质层被蚀刻掉，从而在第二栅极介质层中形成浮栅的底切。去除面具。多晶硅间隔物形成在浮置栅极的侧壁上，其中多晶硅间隔物中的一个填充底切，从而形成尖锐的多晶硅尖端，以提高存储单元的擦除效率。

5. 发明授权

US06664153B2 Method to fabricate a single gate with dual work-functions 失效
标题翻译：制造具有双功能功能的单门的方法
公开(公告)号：US06664153B2
公开(公告)日：2003-12-16
申请号：US10072099
申请日：2002-02-08
申请人： Chew Hoe Ang , Eng Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
发明人： Chew Hoe Ang , Eng Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
IPC分类号： H01L21336
CPC分类号： H01L29/4983 , H01L21/28035
摘要： A method for forming a single gate having a dual work-function is described. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-function and whereby a central portion of the gate electrode not doped has a second work-function to complete formation of a single gate having multiple work-functions in the fabrication of integrated circuits.
摘要翻译：描述了一种形成具有双功能功能的单门的方法。在基板上形成覆盖栅介质层的栅电极。栅电极的侧壁被选择性掺杂，由此掺杂侧壁具有第一功函数，并且由此未掺杂的栅电极的中心部分具有第二功函数，以在制造中完成形成具有多个功函数的单个栅极的集成电路。

6. 发明授权

US06429109B1 Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate 有权
标题翻译：通过在氧化物和栅极之间使用牺牲金属来形成高k电介质和硅化物以减少多余的方法
公开(公告)号：US06429109B1
公开(公告)日：2002-08-06
申请号：US10017953
申请日：2001-12-14
申请人： Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen , Chew Hoe Ang , Eng Hua Lim , Randall Cha
发明人： Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen , Chew Hoe Ang , Eng Hua Lim , Randall Cha
IPC分类号： H01L214763
CPC分类号： H01L21/28194 , H01L21/28097 , H01L21/28176 , H01L21/28238 , H01L29/513 , H01L29/517
摘要： A method of forming a gate comprising the following steps. A substrate is provided. A pre-gate structure is formed over the substrate. The pregate structure includes a sacrificial metal layer between an upper gate conductor layer and a lower gate dielectric layer. The pre-gate structure is annealed to form the gate. The gate comprising: an upper silicide layer formed from a portion of the sacrificial metal layer and a portion of the upper gate conductor layer from the anneal; and a lower metal oxide layer formed from a portion of the gate dielectric layer and a portion of the sacrificial metal layer from the anneal.
摘要翻译：一种形成浇口的方法，包括以下步骤。提供基板。在衬底上形成预栅极结构。预栅结构包括在上栅极导体层和下栅极介电层之间的牺牲金属层。预栅结构退火形成栅极。该栅极包括：由牺牲金属层的一部分形成的上硅化物层和来自退火的上部栅极导体层的一部分; 以及由栅极电介质层的一部分和来自退火的牺牲金属层的一部分形成的下部金属氧化物层。

7. 发明授权

US06828082B2 Method to pattern small features by using a re-flowable hard mask 有权
标题翻译：通过使用可重新流动的硬掩模来绘制小特征的方法
公开(公告)号：US06828082B2
公开(公告)日：2004-12-07
申请号：US10072102
申请日：2002-02-08
申请人： Chew-Hoe Ang , Eng Hua Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
发明人： Chew-Hoe Ang , Eng Hua Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： G03F700
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/31144
摘要： A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “1”. The re-flowed first opening lower width “1” being less than the pre-reflowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “1”. Removing the patterned, re-flowed masking layer. A small feature material is then formed within the second opening and any excess small feature material above the etched spacing layer is removed. The etched spacing layer is removed to form the small feature comprised of the small feature material.
摘要翻译：一种形成小特征的方法，包括以下步骤。提供其上形成有介电层的基板。在电介质层上形成间隔层。间隔层的厚度等于要形成的小特征的厚度。在间隔层上形成图案化的可重新流动的掩模层。掩模层具有宽度“L”的第一开口。图案化的可再流过的掩模层被再流动以形成具有较低宽度“1”的具有再流动的第一开口的图案化的再流过的掩蔽层。再流通的第一开口下部宽度“1”小于预先回流的第一开口宽度“L”。使用图案化的再流过的掩模层作为掩模将间隔层蚀刻到介电层，以在蚀刻的间隔层内形成具有等于再流动的第一开口下宽度“1”的宽度的第二开口。去除图案化的再流过的掩蔽层。然后在第二开口内形成小的特征材料，并且去除蚀刻的间隔层上方的任何过量的小特征材料。蚀刻的间隔层被去除以形成由小特征材料组成的小特征。

8. 发明授权

US06297126B1 Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts 失效
标题翻译：氮化硅封装的浅沟槽隔离方法，用于制造具有无边界接触的亚微米器件
公开(公告)号：US06297126B1
公开(公告)日：2001-10-02
申请号：US09351240
申请日：1999-07-12
申请人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
发明人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/76897
摘要： An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.
摘要翻译：具有亚四分之一微米基准规则的在浅沟槽隔离（STI）中制造MOSFET的改进和新工艺包括氮化硅的钝化沟槽盖层。氮化硅钝化沟槽帽用于形成无边界或“非成形”的电触头，而不会减少聚对多晶间距。形成无边界接触，其中接触开口在有源区（P-N结）和无源沟槽隔离区之上的层间电介质（ILD）层中被蚀刻。在接触孔打开期间，利用蚀刻ILD层的选择性蚀刻工艺，而保护性钝化氮化硅沟槽覆盖层保持完好，保护沟槽区域边缘处的P-N结。防止导电钨金属插塞的后续处理被钝化沟槽盖短路。这种在部分凹陷的沟槽隔离方案中与钝化沟槽盖形成无边界接触的方法提高了器件的可靠性，因为它防止了P-N结的电短路并降低了整体的二极管泄漏。此外，在随后的清洁工艺步骤中，使用氮化硅沟槽帽保护下面的STI沟槽氧化物。此外，除了最小化晶体管结漏电外，氮化物盖还可保护STI氧化物免于过度的凹陷形成，并防止STI接缝的暴露。

9. 发明授权

US06228727B1 Method to form shallow trench isolations with rounded corners and reduced trench oxide recess 有权
标题翻译：形成具有圆角和减少的沟槽氧化物凹陷的浅沟槽隔离的方法
公开(公告)号：US06228727B1
公开(公告)日：2001-05-08
申请号：US09405061
申请日：1999-09-27
申请人： Chong Wee Lim , Soh Yun Siah , Eng Hua Lim , Kong-Hean Lee , Chun Hui Low
发明人： Chong Wee Lim , Soh Yun Siah , Eng Hua Lim , Kong-Hean Lee , Chun Hui Low
IPC分类号： H01L21336
CPC分类号： H01L21/3086 , H01L21/31053 , H01L21/31612 , H01L21/32 , H01L21/76232
摘要： A method of fabricating shallow trench isolations has been achieved. A semiconductor substrate is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer is deposited. The silicon nitride layer and the pad oxide layer are patterned to form a hard mask. The openings in the hard mask correspond to planned trenches in the semiconductor substrate. A silicon dioxide layer is deposited overlying the silicon nitride layer and the semiconductor substrate. The silicon dioxide layer is anisotropically etched to form sidewall spacers on the inside of the openings of the hard mask. The semiconductor substrate is etched to form the trenches. The sidewall spacers are etched away. The semiconductor substrate is sputter etched to round the corners of the trenches. An oxide trench lining layer is grown overlying the semiconductor substrate. A trench fill layer is deposited overlying the silicon nitride layer and filling the trenches. The trench fill layer is polished down to the top surface of the silicon nitride layer. The silicon nitride layer is etched away. The trench fill layer and the pad oxide layer are polished down to the top surface of the semiconductor substrate to complete the shallow trench isolation, and the integrated circuit device is completed.
摘要翻译：已经实现了制造浅沟槽隔离的方法。提供半导体衬底。生长覆盖半导体衬底的焊盘氧化物层。沉积氮化硅层。将氮化硅层和焊盘氧化物层图案化以形成硬掩模。硬掩模中的开口对应于半导体衬底中的规划沟槽。沉积氮化硅层和半导体衬底上的二氧化硅层。二氧化硅层被各向异性地蚀刻以在硬掩模的开口的内侧上形成侧壁间隔物。蚀刻半导体衬底以形成沟槽。蚀刻掉侧壁间隔物。对半导体衬底进行溅射蚀刻以使沟槽的角落四周。生长在半导体衬底上的氧化物沟槽衬里层。沉积氮化硅层并填充沟槽的沟槽填充层。沟槽填充层被抛光到氮化硅层的顶表面。蚀刻掉氮化硅层。沟槽填充层和焊盘氧化物层被抛光到半导体衬底的顶表面以完成浅沟槽隔离，并且集成电路器件完成。

10. 发明授权

US6165871A Method of making low-leakage architecture for sub-0.18 .mu.m salicided CMOS device 失效
标题翻译：亚0.18微米水银CMOS器件制造低泄漏架构的方法
公开(公告)号：US6165871A
公开(公告)日：2000-12-26
申请号：US356003
申请日：1999-07-16
申请人： Eng Hua Lim , Chong Wee Lim , Soh Yun Siah , Kong Hean Lee , Pei Ching Lee
发明人： Eng Hua Lim , Chong Wee Lim , Soh Yun Siah , Kong Hean Lee , Pei Ching Lee
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8234
CPC分类号： H01L29/665 , H01L21/76232 , H01L21/823481
摘要： A method for forming a stepped shallow trench isolation is described. A pad oxide layer is deposited on the surface of a semiconductor substrate. A first nitride layer is deposited overlying the pad oxide layer. The first nitride layer is etched through where it is not covered by a mask to provide an opening to the pad oxide layer. A first trench is etched through the pad oxide layer within the opening and into the semiconductor substrate. A second nitride layer is deposited overlying the first nitride layer and filling the first trench. Simultaneously, the second nitride layer is anisotropically etched to form nitride spacers on the sidewalls of the first trench and the semiconductor substrate is etched into where it is not covered by the spacers to form a second trench. Ions are implanted into the semiconductor substrate underlying the second trench. The first and second trenches are filled with an oxide layer. Thereafter, the first nitride and pad oxide layers are removed completing the formation of shallow trench isolation in the fabrication of an integrated circuit device. This nitride spacer STI architecture prevents STI corner oxide recess and enables borderless contact formation. This unique process reduces junction leakage and also reduces contact leakage.
摘要翻译：描述了形成阶梯式浅沟槽隔离的方法。衬垫氧化物层沉积在半导体衬底的表面上。沉积在衬垫氧化物层上的第一氮化物层。蚀刻第一氮化物层，其中未被掩模覆盖，以提供衬垫氧化物层的开口。通过开口内的衬垫氧化物层蚀刻第一沟槽并进入半导体衬底。沉积第二氮化物层，覆盖第一氮化物层并填充第一沟槽。同时，第二氮化物层被各向异性蚀刻以在第一沟槽的侧壁上形成氮化物间隔物，并且半导体衬底被蚀刻到不被间隔物覆盖的区域中以形成第二沟槽。离子被注入到第二沟槽下面的半导体衬底中。第一和第二沟槽填充有氧化物层。此后，去除在制造集成电路器件时完成形成浅沟槽隔离的第一氮化物层和衬垫氧化物层。该氮化物间隔物STI结构防止了STI拐角氧化物凹陷并且实现无边界接触形成。这种独特的工艺可减少结漏电流并减少接触泄漏。

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