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1. 发明申请

WO2012170027A1 METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH IMPLANTATION THROUGH THE SPACERS 审中-公开
标题翻译：用于产生具有通过间隔物移植的场效应晶体管的方法
公开(公告)号：WO2012170027A1
公开(公告)日：2012-12-13
申请号：PCT/US2011/039774
申请日：2011-06-09
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , STMicroelectronics, Inc. , POSSEME, Nicolas , GRENOUILLET, Laurent , LE TIEC, Yannick , LOUBET, Nicolas , VINET, Maud
发明人： POSSEME, Nicolas , GRENOUILLET, Laurent , LE TIEC, Yannick , LOUBET, Nicolas , VINET, Maud
IPC分类号： H01L21/336
CPC分类号： H01L29/66477 , H01L21/2652 , H01L21/26586 , H01L21/823418 , H01L21/84 , H01L29/66545 , H01L29/66628 , H01L29/66772
摘要： The substrate successively comprises a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.
摘要翻译：基板依次包括支撑基板，电绝缘层，半导体材料层和栅极图案。半导体材料层和栅极图案被覆盖层覆盖。第一掺杂杂质通过覆盖层注入到半导体材料层中，以将第一掺杂杂质的最大浓度的厚度置于第一层中。覆盖层被部分地消除，以形成离开源极/漏电极的横向间隔物。

2. 发明申请

WO2014039034A1 METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER ACTIVE REGIONS 审中-公开
标题翻译：用于在有源区域部分地形成隔离斜面的微电子器件制造方法
公开(公告)号：WO2014039034A1
公开(公告)日：2014-03-13
申请号：PCT/US2012/053768
申请日：2012-09-05
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , STMICROELECTRONICS, INC. , GRENOUILLET, Laurent , LE TIEC, Yannick , LOUBET, Nicolas , VINET, Maud , WACQUEZ, Romain
发明人： GRENOUILLET, Laurent , LE TIEC, Yannick , LOUBET, Nicolas , VINET, Maud , WACQUEZ, Romain
IPC分类号： H01L31/0376
CPC分类号： H01L21/76283 , H01L21/26506 , H01L21/26586 , H01L21/30604 , H01L21/3065 , H01L21/3086 , H01L21/76224 , H01L21/76232 , H01L21/84
摘要： A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps : etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, - filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.
摘要翻译：一种在包括第一半导体层，电介质层和第二半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过所述第一半导体层，所述电介质层和所述第一半导体层的厚度的一部分蚀刻沟槽从而在所述第一半导体层中限定所述微电子器件的一个有源区域，在所述沟槽的一个或多个侧壁中的离子注入，在所述第二半导体层的水平处，修改所述晶体学性质和/或所述第二半导体层，注入半导体的化学性质，蚀刻注入的半导体，使得沟槽的至少一部分在有源区的一部分下延伸; - 用介电材料填充沟槽，形成围绕有源区的隔离沟槽，并且包括在有源区域的一部分下延伸的部分。

3. 发明申请

WO2014039033A1 METHOD OF PRODUCING A MICROELECTRONIC DEVICE IN A MONOCRYSTALLINE SEMICONDUCTOR SUBSTRATE WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER AN ACTIVE REGION 审中-公开
标题翻译：在单晶半导体衬底中生产微电子器件的方法，其具有在活性区域下部分形成的隔离斜面
公开(公告)号：WO2014039033A1
公开(公告)日：2014-03-13
申请号：PCT/US2012/053767
申请日：2012-09-05
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , STMICROELECTRONICS, INC. , VINET, Maud , LOUBET, Nicolas , WACQUEZ, Romain
发明人： VINET, Maud , LOUBET, Nicolas , WACQUEZ, Romain
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/3065 , H01L21/31116 , H01L21/76232 , H01L21/76283 , H01L21/823481 , H01L29/04 , H01L29/045 , H01L29/0653 , H01L29/66772
摘要： A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second monocrystalline semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer and the dielectric layer, and such that the trench delimits one active region of the microelectronic device, chemical vapor etching of the second semiconductor layer, at the level of the bottom wall of the trench, according to at least two crystalline planes of the second semiconductor layer such that an etched part of the second semiconductor layer extends under a part of the active region, filling of the trench and of said etched part of the second semiconductor layer with a dielectric material.
摘要翻译：一种在包括第一半导体层，电介质层和第二单晶半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过第一半导体层和电介质层蚀刻沟槽，并且使得沟槽限定根据所述第二半导体层的至少两个晶面，所述微电子器件的一个有源区域，所述第二半导体层的所述第二半导体层的所述第二半导体层的蚀刻部分在所述沟槽的底壁的水平面上进行化学气相蚀刻，在有源区域的一部分下延伸，用介电材料填充沟槽和第二半导体层的所述蚀刻部分。

4. 发明申请

WO2012067625A1 SHALLOW HEAVILY DOPED SEMICONDUCTOR LAYER BY CYCLIC SELECTIVE EPITAXIAL DEPOSITION PROCESS 审中-公开
标题翻译：通过循环选择性外延沉积工艺沉积重金属半导体层
公开(公告)号：WO2012067625A1
公开(公告)日：2012-05-24
申请号：PCT/US2010/057441
申请日：2010-11-19
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , STMICROELECTRONICS, INC. , DESTEFANIS, Vincent , LOUBET, Nicolas
发明人： DESTEFANIS, Vincent , LOUBET, Nicolas
IPC分类号： H01L21/00
CPC分类号： H01L21/0226 , H01L21/02499 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02642
摘要： The deposition method comprises providing a substrate with a first mono-crystalline zone made of a semiconductor material and a second zone made of an insulating material. During a passivation step, a passivation atmosphere is applied on the substrate so as to cover the first zone with doping impurities. During a deposition step, gaseous silicon and/or germanium precursors are introduced and a doped semiconductor film is formed. The semiconductor film is mono-crystalline over the first zone and has a different texture over the second zone. During an etching step, a chloride gaseous precursor is applied on the substrate so as to remove the semiconductor layer over the second zone.
摘要翻译：沉积方法包括提供具有由半导体材料制成的第一单晶区和由绝缘材料制成的第二区的衬底。在钝化步骤期间，钝化气氛被施加在衬底上，以便用掺杂杂质覆盖第一区域。在沉积步骤期间，引入气态硅和/或锗前体并形成掺杂半导体膜。半导体膜在第一区域上是单晶的，并且在第二区域上具有不同的纹理。在蚀刻步骤期间，将氯化物气体前体施加在衬底上，以便在第二区域上移除半导体层。

5. 发明申请

WO2009112510A1 QUANTUM-DOT DEVICE AND POSITION-CONTROLLED QUANTUM-DOT-FABRICATION METHOD 审中-公开
标题翻译：量子装置和位置控制量子制造方法
公开(公告)号：WO2009112510A1
公开(公告)日：2009-09-17
申请号：PCT/EP2009/052840
申请日：2009-03-11
申请人： NXP B.V. , ST MICROELECTRONICS (CROLLES 2) SAS , BIDAL, Gregory , BOEUF, Frederic , LOUBET, Nicolas
发明人： BIDAL, Gregory , BOEUF, Frederic , LOUBET, Nicolas
IPC分类号： H01L29/06
CPC分类号： H01L29/127 , B82Y10/00 , H01L29/66439 , H01L29/7613
摘要： The present invention relates to a method for position-controlled fabrication of a semiconductor quantum dot, the method comprising: providing a substrate (102) of a substrate material; depositing a sacrificial layer (108) of a sacrificial material; depositing an active layer (110) of a semiconductive active material on the sacrificial layer, wherein the substrate, sacrificial and active materials are chosen such that the sacrificial layer is selectively removable with respect to the substrate and the active layer, depositing and patterning a mask layer on the active layer so as to define desired quantum-dot positions in lateral directions, fabricating a lateral access to the sacrificial layer in regions underneath the patterned mask layer; selectively removing, with respect to the substrate and the active layer, the sacrificial layer from underneath the active layer at least under the patterned mask layer; and etching the active layer under the patterned mask layer from underneath the active layer so as to assume a desired quantum-dot shape.
摘要翻译：本发明涉及半导体量子点的位置控制制造方法，该方法包括：提供衬底材料的衬底（102）; 沉积牺牲材料的牺牲层（108）; 在所述牺牲层上沉积半导体活性材料的有源层（110），其中所述衬底，牺牲层和活性材料被选择为使得所述牺牲层相对于所述衬底和所述有源层选择性地可移除，沉积和图案化掩模层，以便在横向方向上限定期望的量子点位置，在图案化掩模层下面的区域中制造对牺牲层的横向访问; 至少在所述图案化掩模层下方，相对于所述衬底和所述有源层选择性地从所述有源层下方去除所述牺牲层; 并且在有源层下方蚀刻图案化掩模层下面的有源层，以便呈现期望的量子点形状。

6. 发明申请

WO2009095813A1 A METHOD FOR FABRICATING A DUAL-ORIENTATION GROUP-IV SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：一种用于制造双重取向基团IV-IV半导体基板的方法
公开(公告)号：WO2009095813A1
公开(公告)日：2009-08-06
申请号：PCT/IB2009/050199
申请日：2009-01-20
申请人： NXP B.V. , ST MICROELECTRONICS SAS , BIDAL, Gregory, F. , PAYET, Fabrice, A. , LOUBET, Nicolas
发明人： BIDAL, Gregory, F. , PAYET, Fabrice, A. , LOUBET, Nicolas
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L29/045 , H01L29/66651 , H01L29/7833
摘要： The present invention relates to method for fabricating a dual-orientation group-IV semiconductor substrate and comprises in addition to performing a masked amorphization on a DSB-like substrate only in first lateral regions of the surface layer, and a solid-phase epitaxial regrowth of the surface layer in only the first lateral regions so as to establish their (100)-orientation. Subsequently, a cover layer on the surface layer is fabricated, followed by fabricating isolation regions, which laterally separate (l lθ)-oriented first lateral regions and (100)-oriented second lateral regions from each other. Then the cover layer is removed in a selective manner with respect to the isolation regions so as to uncover the surface layer in the first and second lateral regions and a refilling of the first and second lateral regions between the isolation regions is performed using epitaxy.
摘要翻译：本发明涉及制备双取向基团IV半导体衬底的方法，并且除了仅在表面层的第一横向区域中在DSB状衬底上进行掩模非晶化之外，还包括固相外延生长仅在第一侧向区域中的表面层，以便建立其（100）取向。随后，制造表面层上的覆盖层，随后制造彼此横向分离（1l）取向的第一横向区域和（100）取向的第二横向区域的隔离区域。然后以相对于隔离区域的选择性方式去除覆盖层，以便露出第一和第二横向区域中的表面层，并且使用外延进行隔离区域之间的第一和第二横向区域的再填充。

7. 发明申请

WO2014172132A1 MULTI-THRESHOLD VOLTAGE SCHEME FOR FULLY DEPLETED SOI MOSFETS 审中-公开
标题翻译：用于完全绝缘的SOI MOSFET的多阈值电压方案
公开(公告)号：WO2014172132A1
公开(公告)日：2014-10-23
申请号：PCT/US2014/033181
申请日：2014-04-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , STMICROELECTRONICS, INC. , GLOBALFOUNDRIES, INC.
发明人： CHENG, Kangguo , DORIS, Bruce, B. , KHAKIFIROOZ, Ali , LIU, Qing , LOUBET, Nicolas , LUNING, Scott
IPC分类号： H01L21/76 , H01L21/8232 , H01L21/8238
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823842 , H01L21/84 , H01L27/092 , H01L27/0922 , H01L27/0924 , H01L27/1203 , H01L27/1211 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/4966
摘要： A method for semiconductor fabrication includes providing (404) channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed (406) for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.
摘要翻译：一种用于半导体制造的方法包括在包括至少一个硅锗（SiGe）沟道区的衬底上提供（404）沟道区，所述衬底包括包括第一区和第二区的多个区域。在第一区域中形成用于第一n型场效应晶体管（NFET）和第一p型场效应晶体管（PFET）的栅极结构（406），在第二区域中形成第二NFET和第二PFET，栅极用于在SiGe沟道区上形成第一PFET的结构。用于第一NFET的栅极结构包括具有第一功函数的栅极材料，并且用于第一PFET，第二NFET和第二PFET的栅极结构包括具有第二功函数的栅极材料，使得提供多阈值电压器件。

8. 发明公开

EP2893558A1 METHOD OF PRODUCING A MICROELECTRONIC DEVICE IN A MONOCRYSTALLINE SEMICONDUCTOR SUBSTRATE WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER AN ACTIVE REGION 有权转让
标题翻译：方法生产电子器件的微型单晶半导体衬底，部分地处于一个主动区域中形成隔离沟槽
公开(公告)号：EP2893558A1
公开(公告)日：2015-07-15
申请号：EP12884191.3
申请日：2012-09-05
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives , STMicroelectronics, Inc.
发明人： VINET, Maud , LOUBET, Nicolas , WACQUEZ, Romain
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/3065 , H01L21/31116 , H01L21/76232 , H01L21/76283 , H01L21/823481 , H01L29/04 , H01L29/045 , H01L29/0653 , H01L29/66772
摘要： A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second monocrystalline semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer and the dielectric layer, and such that the trench delimits one active region of the microelectronic device, chemical vapor etching of the second semiconductor layer, at the level of the bottom wall of the trench, according to at least two crystalline planes of the second semiconductor layer such that an etched part of the second semiconductor layer extends under a part of the active region, filling of the trench and of said etched part of the second semiconductor layer with a dielectric material.

9. 发明公开

EP2718965A1 METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH IMPLANTATION THROUGH THE SPACERS 审中-公开
标题翻译：用于生产具有注入场效应TRANSISTORS由支架
公开(公告)号：EP2718965A1
公开(公告)日：2014-04-16
申请号：EP11867399.5
申请日：2011-06-09
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives , STMicroelectronics, Inc.
发明人： POSSEME, Nicolas , GRENOUILLET, Laurent , LE TIEC, Yannick , LOUBET, Nicolas , VINET, Maud
IPC分类号： H01L21/336
CPC分类号： H01L29/66477 , H01L21/2652 , H01L21/26586 , H01L21/823418 , H01L21/84 , H01L29/66545 , H01L29/66628 , H01L29/66772
摘要： The substrate successively comprises a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.

10. 发明公开

EP2641264A1 SHALLOW HEAVILY DOPED SEMICONDUCTOR LAYER BY CYCLIC SELECTIVE EPITAXIAL DEPOSITION PROCESS 审中-公开
标题翻译：平板状的高掺杂半导体层通过循环选择性外延分离工艺
公开(公告)号：EP2641264A1
公开(公告)日：2013-09-25
申请号：EP10859767.5
申请日：2010-11-19
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives , Stmicroelectronics, Inc.
发明人： DESTEFANIS, Vincent , LOUBET, Nicolas
IPC分类号： H01L21/00
CPC分类号： H01L21/0226 , H01L21/02499 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02642
摘要： The deposition method comprises providing a substrate with a first mono-crystalline zone made of a semiconductor material and a second zone made of an insulating material. During a passivation step, a passivation atmosphere is applied on the substrate so as to cover the first zone with doping impurities. During a deposition step, gaseous silicon and/or germanium precursors are introduced and a doped semiconductor film is formed. The semiconductor film is mono-crystalline over the first zone and has a different texture over the second zone. During an etching step, a chloride gaseous precursor is applied on the substrate so as to remove the semiconductor layer over the second zone.

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