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1. 发明申请

US20120185815A1 METHOD FOR EXTRACTING INFORMATION FOR A CIRCUIT DESIGN 失效
标题翻译：提取电路设计信息的方法
公开(公告)号：US20120185815A1
公开(公告)日：2012-07-19
申请号：US13427516
申请日：2012-03-22
申请人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
发明人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.
摘要翻译：本公开涉及一种用于提取电路设计的信息的方法。该方法可以利用增量提取处理来提取电路设计的一部分的信息。该部分的提取结果可以与先前提取的结果合并，以获得等同于提取整个电路设计的结果。增量提取过程可以识别一组改变的形状，一组受影响的形状以及一组涉及的提取形状。该方法还可以将电路设计分成多个区域，其中两个或更多个区域可以并行处理。

2. 发明授权

US08539428B2 Method for extracting information for a circuit design 失效
标题翻译：电路设计信息提取方法
公开(公告)号：US08539428B2
公开(公告)日：2013-09-17
申请号：US13427516
申请日：2012-03-22
申请人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
发明人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.
摘要翻译：本公开涉及一种用于提取电路设计的信息的方法。该方法可以利用增量提取处理来提取电路设计的一部分的信息。该部分的提取结果可以与先前提取的结果合并，以获得等同于提取整个电路设计的结果。增量提取过程可以识别一组改变的形状，一组受影响的形状以及一组涉及的提取形状。该方法还可以将电路设计分成多个区域，其中两个或更多个区域可以并行处理。

3. 发明申请

US20120180013A1 METHOD FOR EXTRACTING INFORMATION FOR A CIRCUIT DESIGN 失效
标题翻译：提取电路设计信息的方法
公开(公告)号：US20120180013A1
公开(公告)日：2012-07-12
申请号：US13427486
申请日：2012-03-22
申请人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
发明人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method includes establishing a reflexive relationship between a plurality of design shapes corresponding to a plurality of circuit components in the circuit design. The method includes receiving a design change for at least one design shape of the plurality of design shapes. The method includes identifying a set of changed shapes, a set of affected shapes, and a set of involved shapes. The method includes extracting at least one of a capacitance, an inductance or a resistance for the updated circuit design based on at least one of the set of changed shapes, the set of affected shapes and the set of involved shapes. The method includes updating the plurality of circuit components in the circuit design based on at least one of the set of changed shapes and the set of affected shapes.
摘要翻译：本公开涉及一种用于提取电路设计的信息的方法。该方法包括在与电路设计中的多个电路部件相对应的多个设计形状之间建立反射关系。该方法包括接收多个设计形状的至少一个设计形状的设计变化。该方法包括识别一组改变的形状，一组受影响的形状以及一组涉及的形状。该方法包括基于变化的形状，受影响的形状的集合和所涉及的形状的集合中的至少一个来提取用于更新的电路设计的电容，电感或电阻中的至少一个。所述方法包括基于所述一组改变的形状和所述一组受影响的形状中的至少一个来更新所述电路设计中的所述多个电路部件。

4. 发明申请

US20100251198A1 METHOD FOR EXTRACTING INFORMATION FOR A CIRCUIT DESIGN 失效
标题翻译：提取电路设计信息的方法
公开(公告)号：US20100251198A1
公开(公告)日：2010-09-30
申请号：US12415266
申请日：2009-03-31
申请人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
发明人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.
摘要翻译：本公开涉及一种用于提取电路设计的信息的方法。该方法可以利用增量提取处理来提取电路设计的一部分的信息。该部分的提取结果可以与先前提取的结果合并，以获得等同于提取整个电路设计的结果。增量提取过程可以识别一组改变的形状，一组受影响的形状以及一组涉及的提取形状。该方法还可以将电路设计分成多个区域，其中两个或更多个区域可以并行处理。

5. 发明授权

US08612918B2 Method for extracting information for a circuit design 失效
标题翻译：电路设计信息提取方法
公开(公告)号：US08612918B2
公开(公告)日：2013-12-17
申请号：US13427486
申请日：2012-03-22
申请人： David J. Widiger , Ronald D. Rose , Sandy K Kao , Lewis W Dewey, III , Gerald F Plumb
发明人： David J. Widiger , Ronald D. Rose , Sandy K Kao , Lewis W Dewey, III , Gerald F Plumb
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method includes establishing a reflexive relationship between a plurality of design shapes corresponding to a plurality of circuit components in the circuit design. The method includes receiving a design change for at least one design shape of the plurality of design shapes. The method includes identifying a set of changed shapes, a set of affected shapes, and a set of involved shapes. The method includes extracting at least one of a capacitance, an inductance or a resistance for the updated circuit design based on at least one of the set of changed shapes, the set of affected shapes and the set of involved shapes. The method includes updating the plurality of circuit components in the circuit design based on at least one of the set of changed shapes and the set of affected shapes.
摘要翻译：本公开涉及一种用于提取电路设计的信息的方法。该方法包括在与电路设计中的多个电路部件相对应的多个设计形状之间建立反射关系。该方法包括接收多个设计形状的至少一个设计形状的设计变化。该方法包括识别一组改变的形状，一组受影响的形状以及一组涉及的形状。该方法包括基于变化的形状，受影响的形状的集合和所涉及的形状的集合中的至少一个来提取用于更新的电路设计的电容，电感或电阻中的至少一个。所述方法包括基于所述一组改变的形状和所述一组受影响的形状中的至少一个来更新所述电路设计中的所述多个电路部件。

6. 发明授权

US08645899B2 Method for extracting information for a circuit design 失效
标题翻译：电路设计信息提取方法
公开(公告)号：US08645899B2
公开(公告)日：2014-02-04
申请号：US12415266
申请日：2009-03-31
申请人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
发明人： David J. Widiger , Ronald D. Rose , Sandy K. Kao , Lewis W. Dewey, III , Gerald F. Plumb
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.
摘要翻译：本公开涉及一种用于提取电路设计的信息的方法。该方法可以利用增量提取处理来提取电路设计的一部分的信息。该部分的提取结果可以与先前提取的结果合并，以获得等同于提取整个电路设计的结果。增量提取过程可以识别一组改变的形状，一组受影响的形状以及一组涉及的提取形状。该方法还可以将电路设计分成多个区域，其中两个或更多个区域可以并行处理。

7. 发明申请

US20090281781A1 METHOD AND APPARATUS FOR GENERATING ADAPTIVE NOISE AND TIMING MODELS FOR VLSI SIGNAL INTEGRITY ANALYSIS 审中-公开
标题翻译：用于生成用于VLSI信号完整性分析的自适应噪声和时序模型的方法和装置
公开(公告)号：US20090281781A1
公开(公告)日：2009-11-12
申请号：US12115977
申请日：2008-05-06
申请人： Ronald D. Rose , Sanjay Upreti
发明人： Ronald D. Rose , Sanjay Upreti
IPC分类号： G06F9/455
CPC分类号： G06F17/5036 , G06F11/261
摘要： A method, apparatus and program product are provided for performing a noise, timing, or other signal integrity simulation of a circuit under test. A simulation cache structure is accessed to retrieve cached simulation results for a first portion of the circuit under test. Simulation is performed on a second portion of the circuit under test to generate simulation results for the second portion. Simulation results are generated for the circuit under test by combining the simulation results for the second portion with the cached simulation results for the first portion.
摘要翻译：提供了一种用于对被测电路进行噪声，定时或其他信号完整性仿真的方法，装置和程序产品。访问模拟缓存结构以检索被测电路的第一部分的缓存仿真结果。在被测电路的第二部分进行仿真以产生第二部分的仿真结果。通过将第二部分的模拟结果与第一部分的缓存模拟结果相结合，为被测电路生成仿真结果。

8. 发明授权

US08640062B2 Rapid estimation of temperature rise in wires due to Joule heating 有权
标题翻译：快速估算由于焦耳加热引起的电线温升
公开(公告)号：US08640062B2
公开(公告)日：2014-01-28
申请号：US13157980
申请日：2011-06-10
申请人： Kanak B. Agarwal , Sani R. Nassif , Ronald D. Rose , Chenggang Xu
发明人： Kanak B. Agarwal , Sani R. Nassif , Ronald D. Rose , Chenggang Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5018
摘要： A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self heating. Fast estimation is important to handle millions of nets at the full-chip level. The mechanism models lateral heat flow by considering longitudinal heat flow along the wire and lateral thermal coupling to the other wires in the same level. Lateral heat flow can have a significant effect on the temperature rise. The mechanism also models vertical heat flow to the substrate and the heat sink by considering thermal conductivities of vias and inter-layer dielectric (ILD). The mechanism efficiently solves the thermal system to enable physical design optimizations (e.g., wire sizing, etc.) for fixing electromigration violations.
摘要翻译：提供了一种用于快速估计由于焦耳加热引起的电线温升的机制。该机构可以快速，准确地估计由于自加热引起的导线温升。快速估计对于在全芯片级处理数百万网络很重要。该机制通过考虑沿着导线的纵向热流动并在同一水平的横向热耦合到另一条导线来模拟横向热流。横向热流可以对温升产生显着影响。该机制还通过考虑通孔和层间电介质（ILD）的热导率来模拟垂直热流到衬底和散热片。该机制有效地解决了热系统，以实现用于固定电迁移违规的物理设计优化（例如，线尺寸等）。

9. 发明授权

US08438001B2 Method and apparatus for improving noise analysis performance 失效
标题翻译：提高噪声分析性能的方法和装置
公开(公告)号：US08438001B2
公开(公告)日：2013-05-07
申请号：US12116248
申请日：2008-05-07
申请人： Anita Natarajan , Ronald D. Rose , Sanjay Upreti
发明人： Anita Natarajan , Ronald D. Rose , Sanjay Upreti
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Method and apparatus for improving performance of noise analysis using a threshold based combination of noise estimation and simulation. The method includes classifying a circuit into one of four defined groups, determining if an input noise is small enough to skip simulation, estimating an output noise wave, scaling down a generated wave by a scaling factor depending on the circuit type, and determining if the estimated output noise is small enough to propagate or instead requires simulation.
摘要翻译：使用基于阈值的噪声估计和模拟组合来提高噪声分析性能的方法和装置。该方法包括将电路分为四个定义的组之一，确定输入噪声是否足够小以跳过仿真，估计输出噪声波，根据电路类型按比例缩放所生成的波，并确定是否估计的输出噪声足够小以传播或需要仿真。

10. 发明申请

US20120317529A1 Rapid Estimation of Temperature Rise in Wires Due to Joule Heating 有权
标题翻译：由于焦耳加热引起的电线温升的快速估计
公开(公告)号：US20120317529A1
公开(公告)日：2012-12-13
申请号：US13157980
申请日：2011-06-10
申请人： Kanak B. Agarwal , Sani R. Nassif , Ronald D. Rose , Chenggang Xu
发明人： Kanak B. Agarwal , Sani R. Nassif , Ronald D. Rose , Chenggang Xu
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5036 , G06F17/5018
摘要： A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self heating. Fast estimation is important to handle millions of nets at the full-chip level. The mechanism models lateral heat flow by considering longitudinal heat flow along the wire and lateral thermal coupling to the other wires in the same level. Lateral heat flow can have a significant effect on the temperature rise. The mechanism also models vertical heat flow to the substrate and the heat sink by considering thermal conductivities of vias and inter-layer dielectric (ILD). The mechanism efficiently solves the thermal system to enable physical design optimizations (e.g., wire sizing, etc.) for fixing electromigration violations.
摘要翻译：提供了一种用于快速估计由于焦耳加热引起的电线温升的机制。该机构可以快速，准确地估计由于自加热引起的导线温升。快速估计对于在全芯片级处理数百万网络很重要。该机制通过考虑沿着导线的纵向热流动并在同一水平的横向热耦合到另一条导线来模拟横向热流。横向热流可以对温升产生显着影响。该机制还通过考虑通孔和层间电介质（ILD）的热导率来模拟垂直热流到衬底和散热片。该机制有效地解决了热系统，以实现用于固定电迁移违规的物理设计优化（例如，线尺寸等）。

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