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1. 发明授权

US06601222B1 Coupled noise estimation and avoidance of noise-failure using global routing information 失效
标题翻译：使用全局路由信息耦合噪声估计和避免噪声故障
公开(公告)号：US06601222B1
公开(公告)日：2003-07-29
申请号：US09687132
申请日：2000-10-13
申请人： Sharad Mehrotra , Parsotam Trikam Patel , David J. Widiger
发明人： Sharad Mehrotra , Parsotam Trikam Patel , David J. Widiger
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F17/5077
摘要： Disclosed is a method for pre-design estimation of coupling noise and avoidance of coupling noise failures in interconnects. An initial routing of a plurality of nets is estimated utilizing global paths. Then, the worst-case and average-case models for various parameters of each net are evaluated. With these models, a noise analysis is completed by which a determination is made whether coupling noise of any one of the nets is above a threshold level for noise-induced failure (i.e., a noise-failure threshold). When it is determined that the estimated coupling noise of a net falls below the noise-failure threshold, a response mechanism is triggered for later implementation during detailed routing of the nets to prevent the coupling noise from reaching the noise-failure threshold.
摘要翻译：公开了一种用于耦合噪声的预设计估计和避免互连中的耦合噪声故障的方法。使用全局路径来估计多个网络的初始路由。然后，对每个网络的各种参数的最坏情况和平均情况模型进行评估。利用这些模型，完成噪声分析，通过该噪声分析确定任何一个网络的耦合噪声是否高于用于噪声引起的故障（即，噪声失效阈值）的阈值电平。当确定网络的估计耦合噪声低于噪声失效阈值时，在网络的详细路由期间触发响应机制以供稍后实现，以防止耦合噪声达到噪声失效阈值。

2. 发明授权

US5831870A Method and system for characterizing interconnect data within an integrated circuit for facilitating parasitic capacitance estimation 失效
标题翻译：用于表征集成电路内的互连数据以便于寄生电容估计的方法和系统
公开(公告)号：US5831870A
公开(公告)日：1998-11-03
申请号：US726722
申请日：1996-10-07
申请人： Alan Charles Folta , Sharad Mehrotra , Parsotam Trikam Patel , Paul Gerard Villarrubia
发明人： Alan Charles Folta , Sharad Mehrotra , Parsotam Trikam Patel , Paul Gerard Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and system for characterizing interconnect data within an integrated circuit in order to facilitate parasitic capacitance estimation is disclosed. An integrated circuit typically includes a substrate layer and several metal layers. In accordance with the method and system of the present invention, an overlapping area of interconnect wires is first identified within the integrated circuit. This overlapping area, which is a polygon, may be formed between the substrate layer and at least one interconnect wire in one of the several metal layers. The overlapping area may also be formed between two interconnect wires, each in a different one of the several metal layers. A netname for the overlapping area is then recorded. Finally, a netname of an interconnect wire in a metal layer that is at the same level of an interconnect wire within the overlapping area and an associated distance from each side of the overlapping area is recorded, for every interconnect wire within the overlapping area. By utilizing these recorded information, the parasitic capacitance of the integrated circuit can be estimated more efficiently.
摘要翻译：公开了一种用于表征集成电路内的互连数据以便于寄生电容估计的方法和系统。集成电路通常包括基底层和几个金属层。根据本发明的方法和系统，首先在集成电路内识别互连线的重叠区域。作为多边形的该重叠区域可以形成在基板层和多个金属层之一中的至少一个互连线之间。重叠区域也可以形成在两个互连线之间，每个布线在几个金属层中的不同的一个中。然后记录重叠区域的网络名称。最后，针对重叠区域内的每个互连线，记录金属层内的互连线的网络名称，该网络位于重叠区域内的互连线的相同电平以及与重叠区域的每一侧相关联的距离。通过利用这些记录的信息，可以更有效地估计集成电路的寄生电容。

3. 发明授权

US06415422B1 Method and system for performing capacitance estimations on an integrated circuit design routed by a global routing tool 失效
标题翻译：在由全局路由工具路由的集成电路设计上执行电容估计的方法和系统
公开(公告)号：US06415422B1
公开(公告)日：2002-07-02
申请号：US09397762
申请日：1999-09-17
申请人： Sharad Mehrotra , Parsotam Trikam Patel
发明人： Sharad Mehrotra , Parsotam Trikam Patel
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method for performing capacitance estimations on an integrated circuit design routed by a global routing tool is disclosed. Routing areas and pin locations of a net within an integrated circuit design are initially obtained from a global routing tool. Common boundaries among the routing areas are then defined. Before the performance of a detailed routing step, congestion information furnished by the global routing tool is utilized to perform probabilistic capacitance calculations for an interconnect that can be routed within the routing areas via the defined common boundaries to connect the pin locations.
摘要翻译：公开了一种用于对由全局路由工具路由的集成电路设计进行电容估计的方法。集成电路设计中的网络的路由区域和引脚位置最初是从全局路由工具获得的。然后定义路由区域之间的公共边界。在执行详细的路由步骤之前，利用由全球路由工具提供的拥塞信息来执行互连的概率电容计算，所述互连可以经由定义的公共边界在路由区域内路由以连接引脚位置。

4. 发明授权

US06467069B2 Timing closure and noise avoidance in detailed routing 失效
标题翻译：详细路由中的定时关闭和避免噪声
公开(公告)号：US06467069B2
公开(公告)日：2002-10-15
申请号：US09737333
申请日：2000-12-15
申请人： Sharad Mehrotra , Parsotam Trikam Patel
发明人： Sharad Mehrotra , Parsotam Trikam Patel
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method for timing and noise analysis in designing data processing chips is provided. The process begins by wiring all unconnected nets in the design and then using a 2½ D capacitance extraction technique built into a detailed router to extract all of the wired nets. The data from the extracted nets is then process using a timing and analysis tool. Optimization programs are then used to generate fixes for any nets in the design which contribute to timing and noise failures. The present invention gives designers the capability of fast and accurate interconnect extraction within the routing tool. In addition, this technique is incremental. Any wiring changes can be quickly re-extracted, since only local information is required for extraction. This incremental capability allows designers to perform quick iterations of wiring, extraction and timing analysis.
摘要翻译：提供了一种设计数据处理芯片的时序和噪声分析方法。该过程开始于将设计中所有未连接网络接线，然后使用内置于详细路由器中的2½D电容提取技术来提取所有有线网络。然后使用定时和分析工具处理来自提取的网络的数据。然后，优化程序用于为设计中的任何网络生成有助于定时和噪声故障的修复。本发明使设计人员能够在路由工具内快速准确的互连提取。此外，这种技术是增量的。任何布线变化都可以快速重新提取，因为只需要提取本地信息。这种增量功能允许设计人员快速地进行布线，提取和时序分析。

5. 发明授权

US06218631B1 Structure for reducing cross-talk in VLSI circuits and method of making same using filled channels to minimize cross-talk 失效
标题翻译：用于减少VLSI电路中串扰的结构及其使用填充通道的方法，以尽量减少串扰
公开(公告)号：US06218631B1
公开(公告)日：2001-04-17
申请号：US09115365
申请日：1998-07-14
申请人： Asmus Hetzel , Erich Klink , Juergen Koehl , Dieter Wendel , Parsotam Trikam Patel
发明人： Asmus Hetzel , Erich Klink , Juergen Koehl , Dieter Wendel , Parsotam Trikam Patel
IPC分类号： H01R1204
CPC分类号： H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure for reducing cross-talk in VLSI circuits is disclosed. By filling voltage and ground metal lines in free or unused channels of VLSI chips and connecting them efficiently to the regular power image of the chip, the line to line coupling through vertical layers is reduced almost to zero and in-layer line to line coupling is also drastically reduced.
摘要翻译：公开了一种用于减少VLSI电路串扰的结构。通过在VLSI芯片的自由或未使用通道中填充电压和接地金属线，并将它们有效地连接到芯片的常规功率图像，通过垂直层的线对线耦合几乎减少到零，并且层间线对线耦合也大幅减少。

6. 发明授权

US06360350B1 Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms 失效
标题翻译：对具有不同形式的设计数据的集成电路设计进行电路分析的方法和系统
公开(公告)号：US06360350B1
公开(公告)日：2002-03-19
申请号：US08944975
申请日：1997-10-07
申请人： Carol Ivash Gabele , Stephen Thomas Quay , Paul Gerard Villarrubia , Parsotam Trikam Patel , Jean-Paul Watson
发明人： Carol Ivash Gabele , Stephen Thomas Quay , Paul Gerard Villarrubia , Parsotam Trikam Patel , Jean-Paul Watson
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method for performing circuit analysis on an integrated-circuit design having design data available in different forms is disclosed. In accordance with the method and system of the present invention, the integrated-circuit design includes multiple networks, and the different forms of design data may appear within one of the networks. For all of the networks within the integrated-circuit design, different forms of design data are categorized into at least three databases. The first of the at least three databases may contain three-dimensional extraction information, the second of the databases may contain wiring information, and the third of the databases may contain pre-wiring information. For each of the networks, a determination is made as to whether or not three-dimensional extraction information is available. In response to a determination that three-dimensional extraction information is available, performing circuit analysis by utilizing the three-dimensional extraction information.
摘要翻译：公开了一种用于对具有不同形式的设计数据的集成电路设计进行电路分析的方法。根据本发明的方法和系统，集成电路设计包括多个网络，并且不同形式的设计数据可以出现在一个网络内。对于集成电路设计中的所有网络，不同形式的设计数据分为至少三个数据库。至少三个数据库中的第一个可能包含三维提取信息，第二个数据库可能包含布线信息，第三个数据库可能包含预接线信息。对于每个网络，确定三维提取信息是否可用。响应于三维提取信息可用的确定，通过利用三维提取信息进行电路分析。

7. 发明授权

US5649170A Interconnect and driver optimization for high performance processors 失效
标题翻译：高性能处理器的互连和驱动优化
公开(公告)号：US5649170A
公开(公告)日：1997-07-15
申请号：US497175
申请日：1995-06-30
申请人： Barbara Alane Chappell , Parsotam Trikam Patel , Phoung Kim Phan , George Anthony Sai Halasz
发明人： Barbara Alane Chappell , Parsotam Trikam Patel , Phoung Kim Phan , George Anthony Sai Halasz
IPC分类号： G06F17/50 , H01L27/02 , H03H11/26
CPC分类号： H01L27/0207 , G06F17/505 , G06F17/5068
摘要： A method for determining an optimal design for wiring interconnect and driver power for a designed target delay begins at the floor planning stages of the chip design and may be repeated during the design process. The designer initially specifies a maximum width that wires are allowed to use and a target delay value. Then the designer gives values to weights used in the calculation of an optimization function G(d,p,w), where d is the delay, p is the power, and w is wire width. An "ideal" slope ##EQU1## is calculated, assuming zero resistance. The designer chooses a slope decrease value from the "ideal" slope value. For each set wire width, the delay (at the proper slope) belonging to that particular wire width is obtained. With these inputs, an optimization program according to the invention is run. This program then calculates values of the function G(d,p,w) for increasing wire pitches, starting with the minimum allowed by the technology. The process continues until (1) the target delay is set by the designer is met, (2) the largest pitch value allowed by the designer is reached, or (3) further calculation will not yield a smaller value for the optimization function.
摘要翻译：用于确定用于设计的目标延迟的布线互连和驱动器功率的最佳设计的方法从芯片设计的平面布置阶段开始，并且可以在设计过程期间重复。设计师最初规定允许使用电线的最大宽度和目标延迟值。然后，设计人员给出了计算优化函数G（d，p，w）时使用的权重值，其中d是延迟，p是功率，w是线宽。一个“理想”的斜坡。设计者从“理想”斜率值中选择斜率减小值。对于每组设置的线宽，获得属于该特定线宽的延迟（以适当的斜率）。利用这些输入，执行根据本发明的优化程序。该程序然后计算用于增加线间距的函数G（d，p，w）的值，从该技术允许的最小值开始。该过程一直持续到（1）设计人员满足目标延迟，（2）达到设计师允许的最大间距值，或者（3）进一步的计算不会产生较小的优化函数值。

8. 发明授权

US06230302B1 Method and system for performing timing analysis on an integrated circuit design 失效
标题翻译：用于对集成电路设计进行定时分析的方法和系统
公开(公告)号：US06230302B1
公开(公告)日：2001-05-08
申请号：US09119271
申请日：1998-07-20
申请人： Carol Ivash Gabele , Stephen Thomas Quay , Paul Gerard Villarrubia , Parsotam Trikam Patel , Alexander Koos Spencer
发明人： Carol Ivash Gabele , Stephen Thomas Quay , Paul Gerard Villarrubia , Parsotam Trikam Patel , Alexander Koos Spencer
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A method and system for performing timing analysis on an integrated circuit design are disclosed. It is always advantageous to be able to conveniently perform a timing analysis on the entire IC design at any stage of the design process in order to gain more accurate timing information about the design. However, at an early stage of the design process, the available physical circuit data are often incomplete, not to mention these preliminary data are usually of a lower quality as far as capability of providing an accurate RC delay and capacitance estimation is concerned. To make the best usage of the preliminary data, the present disclosure describes a method of performing a fleeting timing analysis that can be very useful during an early floor planning stage of the design process when there is no opportunity to buffer or widen any exceptionally long interconnect wires within the IC circuit design. As a result, much faster design turn-around time may be achieved because buffer insertion need not be run for every new pass of the physical circuit design data.
摘要翻译：公开了一种用于对集成电路设计进行定时分析的方法和系统。能够方便地在设计过程的任何阶段对整个IC设计进行时序分析，以便获得关于设计的更准确的时序信息。然而，在设计过程的早期阶段，可用的物理电路数据通常是不完整的，更不用说，就提供准确的RC延迟和电容估计的能力而言，这些初步数据通常质量较差。为了最佳地利用初步数据，本公开描述了一种执行短暂定时分析的方法，其在设计过程的早期楼层规划阶段非常有用，当不存在缓冲或加宽任何特别长的互连电线内IC电路设计。因此，可以实现更快的设计周转时间，因为不需要为物理电路设计数据的每个新的通过运行缓冲器插入。

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