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1. 发明授权

US5740109A Non-linear charge pump 失效
标题翻译：非线性电荷泵
公开(公告)号：US5740109A
公开(公告)日：1998-04-14
申请号：US703173
申请日：1996-08-23
申请人： Bruce L. Morton , Yangming Su , Kuo-Tung Chang
发明人： Bruce L. Morton , Yangming Su , Kuo-Tung Chang
IPC分类号： G11C16/30 , G11C11/34 , G05F1/10 , G11C7/00
CPC分类号： G11C16/30
摘要： A non-linear charge pump (1120) provides various voltages for use in a nonvolatile memory (400) and operates at low power supply voltages. The non-linear charge pump (1120) includes at least two non-linear voltage doubling stages (1132, 1134), which allows a capacitor formed with relatively thin gate oxide in a first stage (1132) to be made larger than a capacitor formed using relatively thick gate oxide in a second stage (1134). An output of a last voltage doubling stage (1136) is then input to a linear stage (1150) to generate a precise voltage. Another charge pump (1140) including non-linear stages (1142, 1144) followed by a linear stage (1146) is used to generate a reference voltage for the main non-linear charge pump (1130). The nonlinear stage (1130) includes a special bulk biasing circuit to bias the bulk of a transistor (1285) on the output side of the charging circuit (1284, 1285, 1286, 1287) continuously to prevent forward biasing the parasitic drain-bulk diode.
摘要翻译：非线性电荷泵（1120）提供用于非易失性存储器（400）的各种电压并且在低电源电压下操作。非线性电荷泵（1120）包括至少两个非线性倍压级（1132,1134），其允许在第一级（1132）中形成有较薄栅极氧化物的电容器大于形成的电容器在第二阶段（1134）中使用相对厚的栅极氧化物。然后将最后的倍压级（1136）的输出输入到线性级（1150）以产生精确的电压。使用包括非线性级（1142,1144）和随后的线性级（1146）的另一个电荷泵（1140）来产生主非线性电荷泵（1130）的参考电压。非线性级（1130）包括特殊的体偏置电路，以连续地偏置充电电路（1284,1285,1286,1287）的输出侧的晶体管（1285）的体积，以防止寄生漏 - 体二极管。

2. 发明授权

US5754482A Memory using undecoded precharge for high speed data sensing 失效
标题翻译：内存使用未编码的预充电用于高速数据传感
公开(公告)号：US5754482A
公开(公告)日：1998-05-19
申请号：US845097
申请日：1997-04-21
申请人： Jeffrey Yangming Su , Bruce Lee Morton , Chad Steven Gallun
发明人： Jeffrey Yangming Su , Bruce Lee Morton , Chad Steven Gallun
IPC分类号： G11C16/06 , G11C7/12 , G11C16/24 , G11C16/28 , G11C16/04
CPC分类号： G11C16/28 , G11C16/24 , G11C7/12
摘要： A memory (400) returns all bit lines to a predetermined voltage level optimum for subsequent fast sensing. The memory (400) includes precharge circuitry (106, 108, 110) which begins the precharge operation during the latching phase of a prior access. The precharge circuitry (106, 108, 110) precharges all bit lines, rather than a selected bit line, to the predetermined voltage level prior to address decoding. In order to prevent "walk-up", the memory (400) includes circuitry such as a switched capacitor (138, 140) which draws current from the bit lines to reduce the voltage on a bit line which drove a logic high level in an earlier cycle or which had an increased voltage due to capacitive cross-coupling to an adjacent bit line. The memory (400) may also include devices such as transmission gates (142, 144, 146) to couple together adjacent bit lines and thereby more evenly distribute the precharging.
摘要翻译：存储器（400）将所有位线返回到用于随后的快速感测最佳的预定电压电平。存储器（400）包括在先前访问的锁存阶段期间开始预充电操作的预充电电路（106,108,110）。在地址解码之前，预充电电路（106,108,110）将所有位线而不是所选择的位线预充电到预定电压电平。为了防止“走动”，存储器（400）包括诸如开关电容器（138,140）的电路，其从位线吸取电流以减少位线上的电压，从而驱动逻辑高电平或者由于与相邻位线的电容性交叉耦合而具有增加的电压。存储器（400）还可以包括诸如用于将相邻位线耦合在一起的传输门（142,144,146）的装置，从而更均匀地分配预充电。

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