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1. 发明授权

US09046909B2 On-chip regulator with variable load compensation 有权
标题翻译：具有可变负载补偿的片上调节器
公开(公告)号：US09046909B2
公开(公告)日：2015-06-02
申请号：US14241843
申请日：2012-08-31
申请人： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
发明人： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
IPC分类号： G05F1/10 , G05F1/46 , G11C5/14
CPC分类号： G05F1/462 , G11C5/147
摘要： An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
摘要翻译：集成电路包括用于提供调节电压的电压调节器和耦合到未终端传输线的数据输出。该电路根据数据从电压调节器抽取可变量的功率。电压调节器包括用于提供数据转变相关电流的第一电流产生电路。

2. 发明申请

US20140210545A1 ON-CHIP REGULATOR WITH VARIABLE LOAD COMPENSATION 有权
标题翻译：具有可变负载补偿的片上稳压器
公开(公告)号：US20140210545A1
公开(公告)日：2014-07-31
申请号：US14241843
申请日：2012-08-31
申请人： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
发明人： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
IPC分类号： G05F1/46
CPC分类号： G05F1/462 , G11C5/147
摘要： An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
摘要翻译：集成电路包括用于提供调节电压的电压调节器和耦合到未终端传输线的数据输出。该电路根据数据从电压调节器抽取可变量的功率。电压调节器包括用于提供数据转变相关电流的第一电流产生电路。

3. 发明授权

US09165615B2 Coded differential intersymbol interference reduction 有权
标题翻译：编码差分符号间干扰减少
公开(公告)号：US09165615B2
公开(公告)日：2015-10-20
申请号：US13636515
申请日：2011-03-14
申请人： Amir Amirkhany , Aliazam Abbasfar , Kambiz Kaviani , Wendemagegnehu Beyene , Carl Werner
发明人： Amir Amirkhany , Aliazam Abbasfar , Kambiz Kaviani , Wendemagegnehu Beyene , Carl Werner
IPC分类号： G11C8/00 , G11C7/10 , G11C7/02
CPC分类号： G11C7/1006 , G11C7/02
摘要： Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of the M-links.
摘要翻译：编码器和解码器电路，用于对一系列代码字进行编码和解码一系列数据字。数据字包括L个符号。代码字包括M个符号，其中M大于L.一组紧密耦合的M个链路，用于在每一个码字序列中传送相应的符号。选择码字使得在一系列码字中的每两个连续码字之间，在M链路的子集上出现从低到高和高到低的相等数量的转换。

4. 发明申请

US20120187978A1 Methods and Circuits for Calibrating Multi-Modal Termination Schemes 有权
标题翻译：用于校准多模式终端方案的方法和电路
公开(公告)号：US20120187978A1
公开(公告)日：2012-07-26
申请号：US13349226
申请日：2012-01-12
申请人： Hajee Mohammed Shuaeb Fazeel , Amir Amirkhany , Gundlapalli Shanmukha Srinivas , Chaofeng Huang
发明人： Hajee Mohammed Shuaeb Fazeel , Amir Amirkhany , Gundlapalli Shanmukha Srinivas , Chaofeng Huang
IPC分类号： H03K19/003
CPC分类号： H03K19/017545 , G11C29/025 , G11C29/028 , H03K19/018514 , H03K19/018564
摘要： Disclosed are methods and circuits that support different on-die termination (ODT) schemes for a plurality of signaling schemes using a relatively small number of external calibration pads. These methods and circuits develop control signals for calibrating any of multiple termination schemes that might be used by associated communication circuits. The ODT control circuits, entirely or predominantly instantiated on-die, share circuit resources employed in support of the different termination schemes to save die area.
摘要翻译：公开了使用相对较少数量的外部校准焊盘来支持用于多个信令方案的不同的管芯端接（ODT）方案的方法和电路。这些方法和电路开发用于校准可能由相关联的通信电路使用的多个终止方案中的任何一个的控制信号。 ODT控制电路，完全或主要实例化的裸片，共享用于支持不同终端方案的电路资源，以节省芯片面积。

5. 发明申请

US20110184999A1 Linear Transformation Circuit 审中-公开
标题翻译：线性变换电路
公开(公告)号：US20110184999A1
公开(公告)日：2011-07-28
申请号：US13083473
申请日：2011-04-08
申请人： Aliazam Abbasfar , Amir Amirkhany , Vladimir Stojanovic , Mark A. Horowitz
发明人： Aliazam Abbasfar , Amir Amirkhany , Vladimir Stojanovic , Mark A. Horowitz
IPC分类号： G06F17/14
CPC分类号： G06J1/00
摘要： A first device includes a linear transformation circuit to implement multiplication by a matrix D. The linear transformation circuit as an input to receive a vector having N digital values and an output to output N first output signals. The linear transformation circuit optionally includes a sign-adjustment circuit to adjust signs of a subset including at least M of the N first output signals in accordance with a set of coefficients H. The linear transformation circuit includes a digital-to-analog conversion (DAC) circuit coupled to the output of the sign-adjustment circuit. Outputs from the DAC circuit are summed to produce an output.
摘要翻译：第一装置包括用矩阵D进行乘法的线性变换电路。线性变换电路作为用于接收具有N个数字值的矢量和输出以输出N个第一输出信号的输入。线性变换电路可选地包括符号调整电路，用于根据一组系数H来调整包括至少M个N个第一输出信号的子集的符号。线性变换电路包括数模转换（DAC））电路耦合到符号调节电路的输出。来自DAC电路的输出相加以产生输出。

6. 发明授权

US08917783B2 Resonance mitigation for high-speed signaling 有权
标题翻译：高速信令的共振减轻
公开(公告)号：US08917783B2
公开(公告)日：2014-12-23
申请号：US13129998
申请日：2009-12-03
申请人： Farshid Aryanfar , Aliazam Abbasfar , Amir Amirkhany
发明人： Farshid Aryanfar , Aliazam Abbasfar , Amir Amirkhany
IPC分类号： H04L27/00 , H04L25/02 , H04L25/03
CPC分类号： H04L25/0272 , H04L25/03878
摘要： The frequency response of a first component signal path of a differential signaling link is adjusted to off-set a notch in the frequency response from a corresponding notch in the frequency response of a second component signal path of the differential signaling link.
摘要翻译：差分信号链路的第一分量信号路径的频率响应被调整为在差分信令链路的第二分量信号路径的频率响应中的相应陷波的频率响应中偏移一个陷波。

7. 发明授权

US08139675B2 Multi-tone system with oversampled precoders 失效
标题翻译：具有过采样预编码器的多音系统
公开(公告)号：US08139675B2
公开(公告)日：2012-03-20
申请号：US12907937
申请日：2010-10-19
申请人： Vladimir M. Stojanovic , Amir Amirkhany , Jared L. Zerbe
发明人： Vladimir M. Stojanovic , Amir Amirkhany , Jared L. Zerbe
IPC分类号： H04L27/00
CPC分类号： H04L25/03343 , H04L27/2637
摘要： A multi-tone system includes a data transmission circuit with an interface for receiving a data stream for transmission, a data steam splitter that splits the data stream to produce multiple substreams and a plurality of parallel data preparation circuits. Each data preparation circuit prepares a respective substream for transmission and generates a respective sub-channel signal. At least a first data preparation circuit of the plurality of parallel data preparation circuits includes a first analog filter for filtering a first substream. The first analog filter operates at a sample rate greater than the respective symbol rate of the first substream. The first analog filter provides pre-emphasis of the respective sub-channel signal and attenuation of signals outside of a respective band of frequencies corresponding to the respective sub-channel signal. The data transmission circuit also includes a combiner for combining respective sub-channel signals to generate a data transmission signal.
摘要翻译：多音系统包括具有用于接收用于传输的数据流的接口的数据传输电路，分割数据流以产生多个子流的数据蒸汽分配器和多个并行数据准备电路。每个数据准备电路准备相应的子流进行传输，并产生相应的子信道信号。多个并行数据准备电路的至少第一数据准备电路包括用于对第一子流进行滤波的第一模拟滤波器。第一模拟滤波器以大于第一子流的相应符号率的采样率操作。第一模拟滤波器提供相应子信道信号的预加重和对应于相应子信道信号的相应频带之外的信号的衰减。数据传输电路还包括用于组合各个子信道信号以产生数据传输信号的组合器。

8. 发明申请

US20110150051A1 Multi-Tone System with Oversampled Precoders 失效
标题翻译：带过采样预编码器的多音系统
公开(公告)号：US20110150051A1
公开(公告)日：2011-06-23
申请号：US12907937
申请日：2010-10-19
申请人： Vladimir M. Stojanovic , Amir Amirkhany , Jared L. Zerbe
发明人： Vladimir M. Stojanovic , Amir Amirkhany , Jared L. Zerbe
IPC分类号： H04B1/38
CPC分类号： H04L25/03343 , H04L27/2637
摘要： A multi-tone system includes a data transmission circuit with an interface for receiving a data stream for transmission, a data steam splitter that splits the data stream to produce multiple substreams and a plurality of parallel data preparation circuits. Each data preparation circuit prepares a respective substream for transmission and generates a respective sub-channel signal. At least a first data preparation circuit of the plurality of parallel data preparation circuits includes a first analog filter for filtering a first substream. The first analog filter operates at a sample rate greater than the respective symbol rate of the first substream. The first analog filter provides pre-emphasis of the respective sub-channel signal and attenuation of signals outside of a respective band of frequencies corresponding to the respective sub-channel signal. The data transmission circuit also includes a combiner for combining respective sub-channel signals to generate a data transmission signal.
摘要翻译：多音系统包括具有用于接收用于传输的数据流的接口的数据传输电路，分割数据流以产生多个子流的数据蒸汽分配器和多个并行数据准备电路。每个数据准备电路准备相应的子流进行传输，并产生相应的子信道信号。多个并行数据准备电路的至少第一数据准备电路包括用于对第一子流进行滤波的第一模拟滤波器。第一模拟滤波器以大于第一子流的相应符号率的采样率操作。第一模拟滤波器提供相应子信道信号的预加重和对应于相应子信道信号的相应频带之外的信号的衰减。数据传输电路还包括用于组合各个子信道信号以产生数据传输信号的组合器。

9. 发明授权

US07711063B2 Digital transmitter with data stream transformation circuitry 失效
标题翻译：具数据流转换电路的数字发射机
公开(公告)号：US07711063B2
公开(公告)日：2010-05-04
申请号：US11213353
申请日：2005-08-25
申请人： Elad Alon , Vladimir Stojanovic , Amir Amirkhany
发明人： Elad Alon , Vladimir Stojanovic , Amir Amirkhany
IPC分类号： H04L27/00
CPC分类号： H04L1/0033
摘要： A transmitter with data stream transformation circuitry is described. The transmitter has a first driver and a second driver. Each driver has an output for a respective analog signal. A summation circuit combines respective analog signals from the first driver and the second driver. A data selection circuit processes at least two data streams. Each data stream corresponds to a time sequence of digital data symbols. The data selection circuit selectively couples at least one of the data streams to at least one of the drivers during each time interval of a sequence of time intervals, thereby applying a linear transformation to the data streams. A finite state machine controls the data selection circuit during each time interval of the sequence of time intervals.
摘要翻译：描述了具有数据流转换电路的发射机。变送器具有第一驱动器和第二驱动器。每个驱动器具有相应模拟信号的输出。求和电路组合来自第一驱动器和第二驱动器的相应的模拟信号。数据选择电路处理至少两个数据流。每个数据流对应于数字数据符号的时间序列。在时间序列序列的每个时间间隔期间，数据选择电路将至少一个数据流选择性地耦合到至少一个驱动器，从而对数据流进行线性变换。有限状态机在时间间隔序列的每个时间间隔期间控制数据选择电路。

10. 发明申请

US20060133538A1 Adjustable dual-band link 失效
公开(公告)号：US20060133538A1
公开(公告)日：2006-06-22
申请号：US11022469
申请日：2004-12-22
申请人： Vladimir Stojanovic , Amir Amirkhany , Jared Zerbe
发明人： Vladimir Stojanovic , Amir Amirkhany , Jared Zerbe
IPC分类号： H04L27/20 , H04L27/22
CPC分类号： H04L27/2637 , H04L5/06 , H04L27/2653
摘要： A communication system utilizing an adjustable link has at least a first data transmission circuit including at least a first communication link circuit. The first communication link circuit has a baseband circuit and at least a passband circuit. The baseband circuit corresponds to a baseband sub-channel and the passband circuit corresponds to a passband sub-channel. The first communication link circuit also includes a circuit that distributes a first subset of a data stream having a first symbol rate to the baseband circuit and a second subset of the data stream having a second symbol rate to the passband circuit. The baseband sub-channel and the passband sub-channel are separated by an adjacent guardband of frequencies. The passband carrier frequency is adjusted to define the guardband and the guardband corresponds to a first notch in a channel response of a first communications channel.

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