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1. 发明申请

US20140210545A1 ON-CHIP REGULATOR WITH VARIABLE LOAD COMPENSATION 有权
标题翻译：具有可变负载补偿的片上稳压器
公开(公告)号：US20140210545A1
公开(公告)日：2014-07-31
申请号：US14241843
申请日：2012-08-31
申请人： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
发明人： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
IPC分类号： G05F1/46
CPC分类号： G05F1/462 , G11C5/147
摘要： An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
摘要翻译：集成电路包括用于提供调节电压的电压调节器和耦合到未终端传输线的数据输出。该电路根据数据从电压调节器抽取可变量的功率。电压调节器包括用于提供数据转变相关电流的第一电流产生电路。

2. 发明授权

US09046909B2 On-chip regulator with variable load compensation 有权
标题翻译：具有可变负载补偿的片上调节器
公开(公告)号：US09046909B2
公开(公告)日：2015-06-02
申请号：US14241843
申请日：2012-08-31
申请人： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
发明人： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
IPC分类号： G05F1/10 , G05F1/46 , G11C5/14
CPC分类号： G05F1/462 , G11C5/147
摘要： An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
摘要翻译：集成电路包括用于提供调节电压的电压调节器和耦合到未终端传输线的数据输出。该电路根据数据从电压调节器抽取可变量的功率。电压调节器包括用于提供数据转变相关电流的第一电流产生电路。

3. 发明授权

US08743973B2 Receiver resistor network for common-mode signaling 失效
标题翻译：用于共模信号的接收电阻网络
公开(公告)号：US08743973B2
公开(公告)日：2014-06-03
申请号：US13115838
申请日：2011-05-25
申请人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
发明人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： H04L5/20
摘要： A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.
摘要翻译：接收来自第一和第二对传输线的信号的接收机电路包括第一和第二接口，每个具有第一和第二输入节点以接收相应的信号。接收器电路还包括具有第一，第二，第三和第四电阻元件的电阻器网络。第一和第二电阻元件各自连接在相应接口的输入节点之间。第三和第四电阻元件各自包括串联连接在相应接口的输入节点和电阻器之间的中间节点的一对电阻器。中间节点连接到交流接地。接收器电路还包括差分放大器，其具有分别耦合到第一和第二接口的第一和第二输入以及输出，以提供从在输入节点处接收的信号的共模分量得到的信号。

4. 发明申请

US20130249612A1 METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING 有权
标题翻译：用于同源信号的方法和装置
公开(公告)号：US20130249612A1
公开(公告)日：2013-09-26
申请号：US13523631
申请日：2012-06-14
申请人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
发明人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC分类号： H03L7/00
CPC分类号： H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
摘要： A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
摘要翻译：在各种实施例中描述了低功率，高性能的源同步芯片接口，其提供快速开启并且促进位于不同芯片上的发射机和接收机之间的高信令速率。芯片接口的一些实施例包括：分段的“快速接通”偏置电路，以减少快速上电过程期间的电源振铃; 电流模式逻辑时钟缓冲器在芯片接口的时钟路径中进一步降低电源振铃的影响; 乘法注入锁定振荡器（MILO）时钟发生器，用于从参考时钟产生更高频率的时钟信号; 一个数字控制延时线，可以插入到时钟通路中，以减轻由MILO时钟发生器引起的确定性抖动; 以及用于周期性地重新评估是否安全地重新计算参考时钟域中的数据信号的电路直接用较快的时钟信号。

5. 发明申请

US20110293041A1 Receiver Resistor Network for Common-Mode Signaling 失效
标题翻译：用于共模信号的接收器电阻网络
公开(公告)号：US20110293041A1
公开(公告)日：2011-12-01
申请号：US13115838
申请日：2011-05-25
申请人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
发明人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
IPC分类号： H04L27/00
CPC分类号： H04L5/20
摘要： A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.
摘要翻译：接收来自第一和第二对传输线的信号的接收机电路包括第一和第二接口，每个具有第一和第二输入节点以接收相应的信号。接收器电路还包括具有第一，第二，第三和第四电阻元件的电阻器网络。第一和第二电阻元件各自连接在相应接口的输入节点之间。第三和第四电阻元件各自包括串联连接在相应接口的输入节点和电阻器之间的中间节点的一对电阻器。中间节点连接到交流接地。接收器电路还包括差分放大器，其具有分别耦合到第一和第二接口的第一和第二输入端和输出端，以提供从在输入节点接收的信号的共模分量得到的信号。

6. 发明授权

US08836394B2 Method and apparatus for source-synchronous signaling 有权
标题翻译：源同步信令的方法和装置
公开(公告)号：US08836394B2
公开(公告)日：2014-09-16
申请号：US13523631
申请日：2012-06-14
申请人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
发明人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC分类号： H03L7/00 , H04L7/00 , H04L7/033 , G11C7/10
CPC分类号： H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
摘要： A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
摘要翻译：在各种实施例中描述了低功率，高性能的源同步芯片接口，其提供快速开启并且促进位于不同芯片上的发射机和接收机之间的高信令速率。芯片接口的一些实施例包括：分段的“快速接通”偏置电路，以减少快速上电过程期间的电源振铃; 电流模式逻辑时钟缓冲器在芯片接口的时钟路径中进一步降低电源振铃的影响; 乘法注入锁定振荡器（MILO）时钟发生器，用于从参考时钟产生更高频率的时钟信号; 一个数字控制延时线，可以插入到时钟通路中，以减轻由MILO时钟发生器引起的确定性抖动; 以及用于周期性地重新评估是否安全地重新计算参考时钟域中的数据信号的电路直接用较快的时钟信号。

7. 发明授权

US08588280B2 Asymmetric communication on shared links 有权
标题翻译：共享链路上的不对称通信
公开(公告)号：US08588280B2
公开(公告)日：2013-11-19
申请号：US12809000
申请日：2008-12-19
申请人： Kyung Suk Oh , John Wilson , Frederick A. Ware , WooPoung Kim , Jade M. Kizer , Brian S. Leibowitz , Lei Luo , John Cronan Eble
发明人： Kyung Suk Oh , John Wilson , Frederick A. Ware , WooPoung Kim , Jade M. Kizer , Brian S. Leibowitz , Lei Luo , John Cronan Eble
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： G06F13/4243 , H04L25/4906 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.
摘要翻译：描述通过共享链路在两个设备之间传送双向数据的系统的实施例。在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。数据可以在传输之前被编码为一系列并行码字。每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

8. 发明申请

US20100309964A1 ASYMMETRIC COMMUNICATION ON SHARED LINKS 有权
标题翻译：共享链路上的不对称通信
公开(公告)号：US20100309964A1
公开(公告)日：2010-12-09
申请号：US12809000
申请日：2008-12-19
申请人： Kyung Suk Oh , John Wilson , Frederick Ware , WooPoung Kim , Jade M. Kizer , Brian S. Leibowitz , Lei Luo , John Cronan Eble
发明人： Kyung Suk Oh , John Wilson , Frederick Ware , WooPoung Kim , Jade M. Kizer , Brian S. Leibowitz , Lei Luo , John Cronan Eble
IPC分类号： H04B1/38
CPC分类号： G06F13/4243 , H04L25/4906 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.
摘要翻译：描述通过共享链路在两个设备之间传送双向数据的系统的实施例。在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。数据可以在传输之前被编码为一系列并行码字。每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

9. 发明授权

US08198930B2 Reducing power-supply-induced jitter in a clock-distribution circuit 有权
标题翻译：降低时钟分配电路中的电源引起的抖动
公开(公告)号：US08198930B2
公开(公告)日：2012-06-12
申请号：US12913754
申请日：2010-10-27
申请人： Jared Zerbe , Brian Leibowitz , Lei Luo , John Wilson , Anshuman Bhuyan , Marko Aleksic
发明人： Jared Zerbe , Brian Leibowitz , Lei Luo , John Wilson , Anshuman Bhuyan , Marko Aleksic
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , G06F1/10 , H03K5/1506 , H03K2005/00039 , H03K2005/0013 , H03K2217/0018
摘要： A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a first chain of clock buffers. Note that a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers. The system also couples a second chain of clock buffers in series with the first chain of clock buffers. The system then couples the first voltage source to each clock buffer in the second chain of clock buffers through coupling circuitry. Next, the system adjusts the coupling circuitry so that the change in the first supply voltage from the first voltage source causes a change in a second propagation delay associated with the second chain of the clock buffers, wherein the change in the first propagation delay and the change in the second propagation delay are complementary.
摘要翻译：描述了用于补偿集成电路内的时钟缓冲器链中的电源诱发抖动（PSIJ）的系统。在操作期间，系统将第一电压源的第一电源电压耦合到第一时钟缓冲器链中的每个时钟缓冲器的电源节点。注意，第一电源电压的改变导致与时钟缓冲器的第一链相关联的第一传播延迟的改变。该系统还将第二链时钟缓冲器与第一链时钟缓冲器串联耦合。然后，系统通过耦合电路将第一电压源耦合到第二时钟缓冲器链中的每个时钟缓冲器。接下来，系统调整耦合电路，使得来自第一电压源的第一电源电压的变化引起与时钟缓冲器的第二链相关联的第二传播延迟的改变，其中第一传播延迟和第二传播延迟的变化是互补的。

10. 发明申请

US20110102043A1 REDUCING POWER-SUPPLY-INDUCED JITTER IN A CLOCK-DISTRIBUTION CIRCUIT 有权
标题翻译：在时钟分配电路中减少供电电感器
公开(公告)号：US20110102043A1
公开(公告)日：2011-05-05
申请号：US12913754
申请日：2010-10-27
申请人： Jared Zerbe , Brian Leibowitz , Lei Luo , John Wilson , Anshuman Bhuyan , Marko Aleksic
发明人： Jared Zerbe , Brian Leibowitz , Lei Luo , John Wilson , Anshuman Bhuyan , Marko Aleksic
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , G06F1/10 , H03K5/1506 , H03K2005/00039 , H03K2005/0013 , H03K2217/0018
摘要： A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a first chain of clock buffers. Note that a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers. The system also couples a second chain of clock buffers in series with the first chain of clock buffers. The system then couples the first voltage source to each clock buffer in the second chain of clock buffers through coupling circuitry. Next, the system adjusts the coupling circuitry so that the change in the first supply voltage from the first voltage source causes a change in a second propagation delay associated with the second chain of the clock buffers, wherein the change in the first propagation delay and the change in the second propagation delay are complementary.
摘要翻译：描述了用于补偿集成电路内的时钟缓冲器链中的电源诱发抖动（PSIJ）的系统。在操作期间，系统将第一电压源的第一电源电压耦合到第一时钟缓冲器链中的每个时钟缓冲器的电源节点。注意，第一电源电压的改变导致与时钟缓冲器的第一链相关联的第一传播延迟的改变。该系统还将第二链时钟缓冲器与第一链时钟缓冲器串联耦合。然后，系统通过耦合电路将第一电压源耦合到第二时钟缓冲器链中的每个时钟缓冲器。接下来，系统调整耦合电路，使得来自第一电压源的第一电源电压的变化引起与时钟缓冲器的第二链相关联的第二传播延迟的改变，其中第一传播延迟和第二传播延迟的变化是互补的。

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