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1. 发明申请

US20110184999A1 Linear Transformation Circuit 审中-公开
标题翻译：线性变换电路
公开(公告)号：US20110184999A1
公开(公告)日：2011-07-28
申请号：US13083473
申请日：2011-04-08
申请人： Aliazam Abbasfar , Amir Amirkhany , Vladimir Stojanovic , Mark A. Horowitz
发明人： Aliazam Abbasfar , Amir Amirkhany , Vladimir Stojanovic , Mark A. Horowitz
IPC分类号： G06F17/14
CPC分类号： G06J1/00
摘要： A first device includes a linear transformation circuit to implement multiplication by a matrix D. The linear transformation circuit as an input to receive a vector having N digital values and an output to output N first output signals. The linear transformation circuit optionally includes a sign-adjustment circuit to adjust signs of a subset including at least M of the N first output signals in accordance with a set of coefficients H. The linear transformation circuit includes a digital-to-analog conversion (DAC) circuit coupled to the output of the sign-adjustment circuit. Outputs from the DAC circuit are summed to produce an output.
摘要翻译：第一装置包括用矩阵D进行乘法的线性变换电路。线性变换电路作为用于接收具有N个数字值的矢量和输出以输出N个第一输出信号的输入。线性变换电路可选地包括符号调整电路，用于根据一组系数H来调整包括至少M个N个第一输出信号的子集的符号。线性变换电路包括数模转换（DAC））电路耦合到符号调节电路的输出。来自DAC电路的输出相加以产生输出。

2. 发明授权

US07925686B2 Linear transformation circuit 失效
标题翻译：线性变换电路
公开(公告)号：US07925686B2
公开(公告)日：2011-04-12
申请号：US11311971
申请日：2005-12-19
申请人： Aliazam Abbasfar , Amir Amirkhany , Vladimir Stojanovic , Mark A. Horowitz
发明人： Aliazam Abbasfar , Amir Amirkhany , Vladimir Stojanovic , Mark A. Horowitz
IPC分类号： G06F17/14 , G06F17/15
CPC分类号： G06J1/00
摘要： A first device is described. The first device may include a linear transformation circuit to implement multiplication by a matrix D. The linear transformation circuit may have an input to receive a vector having N digital values and an output to output N first output signals, a sign-adjustment circuit to adjust signs of a subset including at least M of the N first output signals in accordance with a set of coefficients H, and a conversion (DAC) circuit coupled to the sign-adjustment circuit. Outputs from the DAC circuit may be summed to produce an output.
摘要翻译：描述第一设备。第一装置可以包括线性变换电路以实现矩阵D的乘法。线性变换电路可以具有用于接收具有N个数字值的矢量的输入和用于输出N个第一输出信号的输出，用于调整的符号调整电路根据一组系数H包括至少N个N个第一输出信号的子集的符号，以及耦合到符号调整电路的转换（DAC）电路。来自DAC电路的输出可以相加以产生输出。

3. 发明授权

US07133463B1 Linear transformation circuits 失效
标题翻译：线性变换电路
公开(公告)号：US07133463B1
公开(公告)日：2006-11-07
申请号：US11213352
申请日：2005-08-25
申请人： Amir Amirkhany , Vladimir Stojanovic , Elad Alon , Jared LeVan Zerbe , Mark A. Horowitz
发明人： Amir Amirkhany , Vladimir Stojanovic , Elad Alon , Jared LeVan Zerbe , Mark A. Horowitz
IPC分类号： H04L27/04
CPC分类号： G06F17/141 , G06J1/005
摘要： A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of weighted sums of the N digital data symbols. Each respective weighted sum is defined by a respective set of pre-determined weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective weighted sum of the N analog data symbols. Each respective weighted sum is defined by a respective set of pre-determined weighting values in a second matrix.
摘要翻译：变换电路包括第一电路和第二电路。第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。第一电路通过产生N个数字数据符号的加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。每个相应的加权和由第一矩阵中的预定加权值的相应集合定义。第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的各自的加权和。每个相应的加权和由第二矩阵中的预定加权值的相应集合来定义。

4. 发明授权

US07483491B2 Linear transformation circuits 失效
标题翻译：线性变换电路
公开(公告)号：US07483491B2
公开(公告)日：2009-01-27
申请号：US11557101
申请日：2006-11-06
申请人： Amir Amirkhany , Vladimir Stojanovic , Elad Alon , Jared LeVan Zerbe , Mark A. Horowitz
发明人： Amir Amirkhany , Vladimir Stojanovic , Elad Alon , Jared LeVan Zerbe , Mark A. Horowitz
IPC分类号： H04K1/10 , H04L27/28
CPC分类号： G06F17/141 , G06J1/005
摘要： A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of first weighted sums of the N digital data symbols. Each respective first weighted sum is defined by a respective set of pre-determined first weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective second weighted sum of the N analog data symbols. Each respective second weighted sum is defined by a respective set of pre-determined second weighting values in a second matrix.
摘要翻译：变换电路包括第一电路和第二电路。第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。第一电路通过产生N个数字数据符号的第一加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。每个相应的第一加权和由第一矩阵中的预定的第一加权值的相应集合来定义。第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的相应的第二加权和。每个相应的第二加权和由第二矩阵中的预定的第二加权值的相应集合来定义。

5. 发明授权

US07672380B2 Noise-tolerant signaling schemes supporting simplified timing and data recovery 有权
标题翻译：支持简化时序和数据恢复的耐噪声信令方案
公开(公告)号：US07672380B2
公开(公告)日：2010-03-02
申请号：US11895415
申请日：2007-08-23
申请人： Andrew Ho , Vladimir Stojanovic , Fred F. Chen , Elad Alon , Mark A. Horowitz
发明人： Andrew Ho , Vladimir Stojanovic , Fred F. Chen , Elad Alon , Mark A. Horowitz
IPC分类号： H04B3/00 , H04B1/10 , H03D1/04 , H04L5/16
CPC分类号： H04L47/10 , H04L5/20 , H04L25/0276
摘要： Described are communication systems that convey differential and common-mode signals over the same differential channel. Noise-tolerant communication schemes use low-amplitude common-mode signals that are easily rejected by differential receivers, thus allowing for very high differential data rates. Some embodiments employ the common-mode signals to transmit backchannel signals for adjusting the characteristics of the differential transmitter. Backchannel control signals are effectively conveyed even if the forward channel transmitter is so maladjusted that the received differential data is unrecognizable. Systems in accordance with the above-described embodiments obtain these advantages without additional pins or communications channels, and are compatible with both AC-coupled and DC-coupled communications channels. Data coding schemes and corresponding data recovery circuits eliminate the need for complex, high-speed CDR circuits.
摘要翻译：描述了通过相同的差分通道传送差分和共模信号的通信系统。耐噪声通信方案使用容易被差分接收机拒绝的低振幅共模信号，从而允许非常高的差分数据速率。一些实施例采用共模信号来发送用于调整差分发射机的特性的反向信道信号。即使前向信道发射机被调整不正确，接收到的差分数据是无法识别的，反向信道控制信号也被有效地传送。根据上述实施例的系统在没有附加引脚或通信信道的情况下获得这些优点，并且与AC耦合和DC耦合通信信道兼容。数据编码方案和相应的数据恢复电路不需要复杂的高速CDR电路。

6. 发明授权

US07292637B2 Noise-tolerant signaling schemes supporting simplified timing and data recovery 有权
标题翻译：支持简化时序和数据恢复的耐噪声信令方案
公开(公告)号：US07292637B2
公开(公告)日：2007-11-06
申请号：US10739823
申请日：2003-12-17
申请人： Andrew Ho , Vladimir Stojanovic , Fred F. Chen , Elad Alon , Mark A. Horowitz
发明人： Andrew Ho , Vladimir Stojanovic , Fred F. Chen , Elad Alon , Mark A. Horowitz
IPC分类号： H04B3/00 , H04B1/10 , H04B1/18 , H03D1/04
CPC分类号： H04L47/10 , H04L5/20 , H04L25/0276
摘要： Described are communication systems that convey differential and common-mode signals over the same differential channel. Noise-tolerant communication schemes use low-amplitude common-mode signals that are easily rejected by differential receivers, thus allowing for very high differential data rates. Some embodiments employ the common-mode signals to transmit backchannel signals for adjusting the characteristics of the differential transmitter. Backchannel control signals are effectively conveyed even if the forward channel transmitter is so maladjusted that the received differential data is unrecognizable. Systems in accordance with the above-described embodiments obtain these advantages without additional pins or communications channels, and are compatible with both AC-coupled and DC-coupled communications channels. Data coding schemes and corresponding data recovery circuits eliminate the need for complex, high-speed CDR circuits.
摘要翻译：描述了通过相同的差分通道传送差分和共模信号的通信系统。耐噪声通信方案使用容易被差分接收机拒绝的低振幅共模信号，从而允许非常高的差分数据速率。一些实施例采用共模信号来发送用于调整差分发射机的特性的反向信道信号。即使前向信道发射机被调整不正确，接收到的差分数据是无法识别的，反向信道控制信号也被有效地传送。根据上述实施例的系统在没有附加引脚或通信信道的情况下获得这些优点，并且与AC耦合和DC耦合通信信道兼容。数据编码方案和相应的数据恢复电路不需要复杂的高速CDR电路。

7. 发明授权

US09141479B2 Memory system with error detection and retry modes of operation 有权
标题翻译：具有错误检测和重试操作模式的内存系统
公开(公告)号：US09141479B2
公开(公告)日：2015-09-22
申请号：US12940942
申请日：2010-11-05
申请人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
发明人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
IPC分类号： H03M13/00 , G06F11/14 , G06F11/07 , G06F11/10 , H04L1/00 , H04L1/08 , H04L1/18 , G06F11/00
CPC分类号： G06F11/073 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/006 , G06F11/0745 , G06F11/0766 , G06F11/0793 , G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1076 , G06F11/1402 , G06F11/141 , G06F11/1443 , G06F11/20 , G11C29/52 , H03M13/03 , H04L1/0057 , H04L1/0061 , H04L1/08 , H04L1/1809
摘要： A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
摘要翻译：存储器系统包括具有至少一个信号线的链路和控制器。所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。至少一个接收器耦合到链路以接收第二数据。第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

8. 发明授权

US08634452B2 Multiphase receiver with equalization circuitry 有权
标题翻译：具有均衡电路的多相接收器
公开(公告)号：US08634452B2
公开(公告)日：2014-01-21
申请号：US13491508
申请日：2012-06-07
申请人： Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
发明人： Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
IPC分类号： H04B17/00
CPC分类号： H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要： An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.
摘要翻译：集成电路装置包括：第一电路，用于接收与电输入信号的第一数据周期相关联的位，可操作以产生关于与第一数据周期相关联的位的逻辑状态的判定;以及第二电路，用于接收与第电输入信号的第二周期，以产生关于与第二数据周期相关联的位的逻辑状态的判定。均衡电路根据第一电路的输出补偿影响第二电路的符号间干扰，并根据第一电路以外的电路的输出补偿影响第一电路的符号间干扰，该电路可操作以产生关于位的逻辑状态的判定的电气输入信号。

9. 发明授权

US08564328B2 High speed signaling system with adaptive transmit pre-emphasis 有权
公开(公告)号：US08564328B2
公开(公告)日：2013-10-22
申请号：US13476247
申请日：2012-05-21
申请人： Vladimir M. Stojanovic , Andrew C. C. Ho , Anthony Bessios , Fred F. Chen , Elad Alon , Mark A. Horowitz
发明人： Vladimir M. Stojanovic , Andrew C. C. Ho , Anthony Bessios , Fred F. Chen , Elad Alon , Mark A. Horowitz
IPC分类号： H03K19/0175
CPC分类号： H04L25/49 , H04B1/04 , H04B1/0475 , H04B2001/0416 , H04L25/025 , H04L25/028 , H04L25/0282 , H04L25/03019 , H04L25/03343 , H04L25/03885 , H04L25/061 , H04L25/4917 , H04L2025/03363 , H04L2025/03802
摘要： A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

10. 发明申请

US20130136220A1 Clock and Data Recovery Employing Piece-Wise Estimation on the Derivative of the Frequency 有权
标题翻译：时钟和数据恢复采用对频率微分的智慧估计
公开(公告)号：US20130136220A1
公开(公告)日：2013-05-30
申请号：US13674812
申请日：2012-11-12
申请人： Hae-Chang Lee , Thomas H. Greer, III , Jade M. Kizer , Brian S. Leibowitz , Mark A. Horowitz
发明人： Hae-Chang Lee , Thomas H. Greer, III , Jade M. Kizer , Brian S. Leibowitz , Mark A. Horowitz
IPC分类号： H04L7/00
CPC分类号： H04L7/0012 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0331 , H04L7/0337
摘要： A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.
摘要翻译：一种用于执行时钟和数据恢复的系统和方法。根据数据发送器时钟的频率和接收机时钟的频率之间的偏移的变化率的至少三个估计，系统设置恢复的时钟信号的相位。

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