专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130031328A1 TECHNIQUES FOR BALANCING ACCESSES TO MEMORY HAVING DIFFERENT MEMORY TYPES 有权
标题翻译：用于平衡存储器存储不同存储器类型的技术
公开(公告)号：US20130031328A1
公开(公告)日：2013-01-31
申请号：US13191438
申请日：2011-07-26
申请人： Brian Kelleher , Emmett M. Kilgariff , Wayne Yamamoto
发明人： Brian Kelleher , Emmett M. Kilgariff , Wayne Yamamoto
IPC分类号： G06F12/08
CPC分类号： G06F12/0292 , G06F12/06 , G06F12/0607 , G06F12/08 , G06F13/1694 , G06F2212/205 , Y02D10/13 , Y02D10/14
摘要： Embodiments of the present technology are directed toward techniques for balancing memory accesses to different memory types.
摘要翻译：本技术的实施例涉及用于平衡对不同存储器类型的存储器访问的技术。

2. 发明授权

US09529712B2 Techniques for balancing accesses to memory having different memory types 有权
标题翻译：用于平衡具有不同存储器类型的存储器的访问的技术
公开(公告)号：US09529712B2
公开(公告)日：2016-12-27
申请号：US13191438
申请日：2011-07-26
申请人： Brian Kelleher , Emmett M. Kilgariff , Wayne Yamamoto
发明人： Brian Kelleher , Emmett M. Kilgariff , Wayne Yamamoto
IPC分类号： G06F12/08 , G06F12/02 , G06F12/06 , G06F13/16
CPC分类号： G06F12/0292 , G06F12/06 , G06F12/0607 , G06F12/08 , G06F13/1694 , G06F2212/205 , Y02D10/13 , Y02D10/14
摘要： Embodiments of the present technology are directed toward techniques for balancing memory accesses to different memory types.
摘要翻译：本技术的实施例涉及用于平衡对不同存储器类型的存储器访问的技术。

3. 发明授权

US09436969B2 Time slice processing of tessellation and geometry shaders 有权
标题翻译：镶嵌和几何着色器的时间片处理
公开(公告)号：US09436969B2
公开(公告)日：2016-09-06
申请号：US13208256
申请日：2011-08-11
申请人： Ziyad S. Hakura , Emmett M. Kilgariff , Dale L. Kirkland , Johnny S. Rhoades , Cynthia Ann Edgeworth Allison , Karim M. Abdalla
发明人： Ziyad S. Hakura , Emmett M. Kilgariff , Dale L. Kirkland , Johnny S. Rhoades , Cynthia Ann Edgeworth Allison , Karim M. Abdalla
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： One embodiment of the present invention sets forth a technique for redistributing geometric primitives generated by tessellation and geometry shaders for processing by multiple graphics pipelines. Geometric primitives that are generated in a first processing cycle are collected and redistributed more evenly and in smaller tasks to the multiple graphics pipelines for vertex processing in a second processing cycle. The smaller tasks do not exceed the resource limits of a graphics pipeline and the per-vertex processing workloads of the graphics pipelines in the second cycle are balanced and make full use of resources. Therefore, the performance of the tessellation and geometry shaders is improved.
摘要翻译：本发明的一个实施例提出了一种用于重新分配由镶嵌和几何着色器生成的几何图元以用于由多个图形管线进行处理的技术。在第一个处理周期中生成的几何图元在第二个处理周期中被收集并且更均匀地并且在更小的任务中重新分布到用于顶点处理的多个图形流水线。较小的任务不超过图形管道的资源限制，并且第二周期中的图形管道的每顶点处理工作负载平衡并充分利用资源。因此，纹理和几何着色器的性能得到改善。

4. 发明授权

US08237705B2 Hierarchical processor array 有权
标题翻译：分层处理器阵列
公开(公告)号：US08237705B2
公开(公告)日：2012-08-07
申请号：US13270215
申请日：2011-10-10
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T5/00 , G06T15/50 , G06T15/10 , G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

5. 发明申请

US20120176377A1 BLOCK LINEAR MEMORY ORDERING OF TEXTURE DATA TECHNIQUES 有权
标题翻译：块纹线数据技术的线性记忆订单
公开(公告)号：US20120176377A1
公开(公告)日：2012-07-12
申请号：US13422498
申请日：2012-03-16
申请人： Walter E. Donovan , Emmett M. Kilgariff , Karim M. Abdalla , Joel J. McCormack
发明人： Walter E. Donovan , Emmett M. Kilgariff , Karim M. Abdalla , Joel J. McCormack
IPC分类号： G06T15/04 , G06T11/40
CPC分类号： G06T15/04 , G06T1/60
摘要： A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.
摘要翻译：根据本发明的一个实施例的组织用于存储纹理数据的存储器的方法包括访问纹理映射的mipmap级别的大小。可以基于mipmap级别的大小来确定块维度。存储器空间（例如，计算机可读介质）可以在逻辑上被划分为多个整数个可变维度的块。块的尺寸以料滴为单位进行测量，每个料滴的固定尺寸为字节。纹理映射的mipmap级别可以存储在存储器空间中。所述mipmap级别的纹理坐标可以通过确定纹理坐标所驻留的料滴的料滴地址并确定特定料滴中的字节地址来转换为存储器空间的字节地址。

6. 发明申请

US20110090220A1 ORDER-PRESERVING DISTRIBUTED RASTERIZER 有权
标题翻译：订购保存分配的RASTERIZER
公开(公告)号：US20110090220A1
公开(公告)日：2011-04-21
申请号：US12580017
申请日：2009-10-15
申请人： Steven E. Molnar , Emmett M. Kilgariff , Johnny S. Rhoades , Timothy John Purcell , Sean J. Treichler , Ziyad S. Hakura , Franklin C. Crow , James C. Bowman
发明人： Steven E. Molnar , Emmett M. Kilgariff , Johnny S. Rhoades , Timothy John Purcell , Sean J. Treichler , Ziyad S. Hakura , Franklin C. Crow , James C. Bowman
IPC分类号： G06F15/80 , G06T15/00
CPC分类号： G06T15/005 , G06T2210/52
摘要： One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.
摘要翻译：本发明的一个实施例提出了一种用于在保持API原语排序的同时并行渲染图形基元的技术。多个独立的几何单元在不同的图形基元上同时执行几何处理。原始分配方案以每个时钟的多个基元的速率同时向多个光栅化器提供原语，同时保持每个像素的原始排序。多个独立的光栅化器单元在一个或多个图形基元上同时执行光栅化，使得能够每个系统时钟渲染多个基元。

7. 发明授权

US07649538B1 Reconfigurable high performance texture pipeline with advanced filtering 有权
标题翻译：可重构的高性能纹理管道与先进的过滤
公开(公告)号：US07649538B1
公开(公告)日：2010-01-19
申请号：US11556674
申请日：2006-11-03
申请人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J. M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donovan , Emmett M. Kilgariff
发明人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J. M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donovan , Emmett M. Kilgariff
IPC分类号： G06T17/00 , G06T11/40 , G09G5/00 , G09G5/02 , G06K9/40 , G06K9/32 , G06K9/64
CPC分类号： G06T1/60 , G06F3/14 , G06T15/04 , G06T2200/28 , G09G5/026 , G09G5/22 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以快速和有效的方式存储和检索纹素。一个这样的纹理电路为一组像素中的每个像素提供了更多数量的iler骨，特别是当需要三线性或茴香过滤时。对于三线性滤波，在一个时钟周期内针对多个像素检索第一和第二细节级别的纹素。当执行了茴香过滤时，可以在一个时钟周期内为多个像素中的每一个检索多个b骨。

8. 发明授权

US07624255B1 Scheduling program instruction execution by using fence instructions 有权
标题翻译：使用栅栏指令调度程序指令执行
公开(公告)号：US07624255B1
公开(公告)日：2009-11-24
申请号：US11076201
申请日：2005-03-09
申请人： Christian Rouet , Rui M. Bastos , Emmett M. Kilgariff
发明人： Christian Rouet , Rui M. Bastos , Emmett M. Kilgariff
IPC分类号： G06F9/30
CPC分类号： G06F9/30087 , G06F8/445 , G06F9/3836 , G06F9/3867 , G06F9/3885 , G06T15/005
摘要： A system and method controls the scheduling of program instructions included in a shader program for execution by a processing pipeline. One or more fence instructions may be inserted into the shader program. Each fence instruction specifies a constraint that is applied to control the scheduling of another program instruction in the shader program. Controlling the scheduling of program instructions for execution by the processing pipeline may result in a more efficient use of computing resources and improved performance.
摘要翻译：系统和方法控制包括在着色器程序中的程序指令的调度以供处理管线执行。可以将一个或多个栅栏指令插入到着色器程序中。每个栅栏指令都指定一个约束条件，用于控制着色器程序中另一个程序指令的调度。控制由处理流水线执行的程序指令的调度可以导致计算资源的更有效的使用和改进的性能。

9. 发明授权

US07218291B2 Increased scalability in the fragment shading pipeline 有权
标题翻译：增加片段着色管道中的可扩展性
公开(公告)号：US07218291B2
公开(公告)日：2007-05-15
申请号：US10940070
申请日：2004-09-13
申请人： Karim M. Abdalla , Emmett M. Kilgariff , Rui M. Bastos
发明人： Karim M. Abdalla , Emmett M. Kilgariff , Rui M. Bastos
IPC分类号： G09G1/14 , G06T15/50
CPC分类号： G06T11/40 , G06T15/005 , G06T15/50 , G06T15/80
摘要： A fragment processor includes a fragment shader distributor, a fragment shader collector, and a plurality of fragment shader pipelines. Each fragment shader pipeline executes a fragment shader program on a segment of fragments. The plurality of fragment shader pipelines operate in parallel, executing the same or different fragment shader programs. The fragment shader distributor receives a stream of fragments from a rasterization unit and dispatches a portion of the stream of fragments to a selected fragment shader pipeline until the capacity of the selected fragment shader pipeline is reached. The fragment shader distributor then selects another fragment shader pipeline. The capacity of each of the fragment shader pipelines is limited by several different resources. As the fragment shader distributor dispatches fragments, it tracks the remaining available resources of the selected fragment shader pipeline. A fragment shader collector retrieves processed fragments from the plurality of fragment shader pipelines.
摘要翻译：片段处理器包括片段着色器分配器，片段着色器收集器和多个片段着色器管线。每个片段着色器流水线在片段片段上执行片段着色器程序。多个片段着色器管线并行操作，执行相同或不同的片段着色器程序。片段着色器分配器从光栅化单元接收片段流，并将片段流的一部分分派到所选择的片段着色器管线，直到达到所选片段着色器管线的容量。片段着色器分配器然后选择另一个片段着色器管道。每个片段着色器管道的容量受到几个不同的资源的限制。当片段着色器分配器调度片段时，它会跟踪所选片段着色器管道的剩余可用资源。片段着色器收集器从多个片段着色器管道中检索已处理的片段。

10. 发明授权

US07023437B1 System and method for accelerating graphics processing using a post-geometry data stream during multiple-pass rendering 有权
标题翻译：用于在多遍渲染期间使用后几何数据流来加速图形处理的系统和方法
公开(公告)号：US07023437B1
公开(公告)日：2006-04-04
申请号：US10230124
申请日：2002-08-27
申请人： Douglas A. Voorhies , Edward C. Greene , Emmett M. Kilgariff , Svetoslav Tzvetkov
发明人： Douglas A. Voorhies , Edward C. Greene , Emmett M. Kilgariff , Svetoslav Tzvetkov
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： A system and method are provided for accelerating graphics processing utilizing multiple-pass rendering. Initially, geometry operations are performed on graphics data, and the graphics data is stored in memory. During a first rendering pass, various operations take place. For example, the graphics data is read from the memory, and the graphics data is rasterized. Moreover, first z-culling operations are performed utilizing the graphics data. Such first z-culling operations maintain a first occlusion image. During a second rendering pass, the graphics data is read from memory. Still yet, the graphics data is rasterized and second z-culling operations are performed utilizing the graphics data and the first occlusion image. Moreover, visibility operations are performed utilizing the graphics data and a second occlusion image. Raster-processor operations are also performed utilizing the graphics data, during the second rendering pass.
摘要翻译：提供了一种利用多遍渲染加速图形处理的系统和方法。最初，对图形数据进行几何运算，图形数据存储在存储器中。在第一次渲染过程中，进行各种操作。例如，从存储器读取图形数据，并且图形数据被光栅化。此外，利用图形数据执行第一z淘选操作。这样的第一z-淘汰操作保持第一遮挡图像。在第二次渲染过程中，从存储器读取图形数据。仍然，图形数据被光栅化，并且使用图形数据和第一遮挡图像来执行第二z剔除操作。此外，利用图形数据和第二遮挡图像执行可视性操作。在第二次渲染过程中，还使用图形数据执行栅格处理器操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式