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1. 发明申请

US20060092165A1 Memory management system having a forward progress bit 有权
标题翻译：内存管理系统具有前进进度位
公开(公告)号：US20060092165A1
公开(公告)日：2006-05-04
申请号：US10976978
申请日：2004-10-29
申请人： Karim Abdalla , Robert Keller
发明人： Karim Abdalla , Robert Keller
IPC分类号： G09G5/36
CPC分类号： G06F9/52 , G06F12/126 , Y10S707/99952 , Y10S707/99953
摘要： A virtual memory system that maintains a list of pages that are required to be resident in a frame buffer to guarantee the eventual forward progress of a graphics application context running on a graphics system composed of multiple clients. Pages that are required to be in the frame buffer memory are never swapped out of that memory. The required page list can be dynamically sized or fixed sized. A tag file is used to prevent page swapping of a page from the frame buffer that is required to make forward progress. A forward progress indicator signifies that a page faulting client has made forward progress on behalf of a context. The presence of a forward progress indicator is used to clear the tag file, thus enabling page swapping of the previously tagged pages from the frame buffer memory.
摘要翻译：维护需要驻留在帧缓冲器中的页面列表以保证在由多个客户端组成的图形系统上运行的图形应用程序上下文的最终进展的虚拟存储器系统。帧缓冲存储器中所需的页面不会从该存储器中交换出来。所需的页面列表可以动态调整大小或固定大小。标签文件用于防止页面从帧缓冲区中进行页面交换，这是进行进展所需的。前进进度指示符表示页面错误的客户端代表上下文取得了进展。前进进度指示符的存在用于清除标签文件，从而允许从帧缓冲存储器对先前标记的页面进行页面交换。

2. 发明授权

US06535209B1 Data stream splitting and storage in graphics data processing 有权
标题翻译：数据流分割和存储在图形数据处理中
公开(公告)号：US06535209B1
公开(公告)日：2003-03-18
申请号：US09713447
申请日：2000-11-14
申请人： Karim Abdalla , Oren Rubinstein , Ming Benjamin Zhu
发明人： Karim Abdalla , Oren Rubinstein , Ming Benjamin Zhu
IPC分类号： G06T1700
CPC分类号： G06T15/005
摘要： A computer graphics system splits vertex data into first and second streams and stores the streams in separate regions of memory. In a specific embodiment, the first stream includes positional data and the second stream includes non-positional color and texture data. A visibility subsystem uses only the first stream to perform visibility processing, thus reducing bandwidth requirement. The rendering system processes data from subsets, identified by the visibility subsystem, of both streams required to render the visible part of a scene.
摘要翻译：计算机图形系统将顶点数据分解为第一和第二流，并将流存储在存储器的单独区域中。在具体实施例中，第一流包括位置数据，第二流包括非位置颜色和纹理数据。可见性子系统仅使用第一个流来执行可见性处理，从而减少带宽需求。渲染系统处理由可见性子系统识别的子集的数据，呈现呈现场景的可见部分所需的两个流。

3. 发明申请

US20100118043A1 RECONFIGURABLE HIGH-PERFORMANCE TEXTURE PIPELINE WITH ADVANCED FILTERING 有权
标题翻译：可重复使用的高性能纹路管道，具有先进的过滤功能
公开(公告)号：US20100118043A1
公开(公告)日：2010-05-13
申请号：US12689939
申请日：2010-01-19
申请人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J.M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
发明人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J.M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
IPC分类号： G09G5/00
CPC分类号： G06T1/60 , G06F3/14 , G06T15/04 , G06T2200/28 , G09G5/026 , G09G5/22 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以快速和有效的方式存储和检索纹素。一个这样的纹理电路为一组像素中的每个像素提供了更多数量的iler骨，特别是当需要三线性或茴香过滤时。对于三线性滤波，在一个时钟周期内针对多个像素检索第一和第二细节级别的纹素。当执行了茴香过滤时，可以在一个时钟周期内为多个像素中的每一个检索多个b骨。

4. 发明申请

US20080094405A1 SCALABLE SHADER ARCHITECTURE 有权
标题翻译：可分级阴影架构
公开(公告)号：US20080094405A1
公开(公告)日：2008-04-24
申请号：US11957358
申请日：2007-12-14
申请人： Rui BASTOS , Karim Abdalla , Christian Rouet , Michael Toksvig , Johnny Rhoades , Roger Allen , John Tynefield , Emmett Kilgariff , Gary Tarolli , Brian Cabral , Craig Wittenbrink , Sean Treichler
发明人： Rui BASTOS , Karim Abdalla , Christian Rouet , Michael Toksvig , Johnny Rhoades , Roger Allen , John Tynefield , Emmett Kilgariff , Gary Tarolli , Brian Cabral , Craig Wittenbrink , Sean Treichler
IPC分类号： G06F15/80
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译：公开了可扩展着色器架构。根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。着色器包括着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管线，有利于平衡工作负载。着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。

5. 发明申请

US20050225554A1 Scalable shader architecture 有权
标题翻译：可扩展着色器架构
公开(公告)号：US20050225554A1
公开(公告)日：2005-10-13
申请号：US10938042
申请日：2004-09-10
申请人： Rui Bastos , Karim Abdalla , Christian Rouet , Michael Toksvig , Johnny Rhoades , Roger Allen , John Tynefield , Emmett Kilgariff , Gary Tarolli , Brian Cabral , Craig Wittenbrink , Sean Treichler
发明人： Rui Bastos , Karim Abdalla , Christian Rouet , Michael Toksvig , Johnny Rhoades , Roger Allen , John Tynefield , Emmett Kilgariff , Gary Tarolli , Brian Cabral , Craig Wittenbrink , Sean Treichler
IPC分类号： G06T15/00 , G06F15/80 , G06T1/20
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译：公开了可扩展着色器架构。根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。

6. 发明申请

US20060055695A1 Increased scalability in the fragment shading pipeline 有权
标题翻译：增加片段着色管道中的可扩展性
公开(公告)号：US20060055695A1
公开(公告)日：2006-03-16
申请号：US10940070
申请日：2004-09-13
申请人： Karim Abdalla , Emmett Kilgariff , Rui Bastos
发明人： Karim Abdalla , Emmett Kilgariff , Rui Bastos
IPC分类号： G06T15/50
CPC分类号： G06T11/40 , G06T15/005 , G06T15/50 , G06T15/80
摘要： A fragment processor includes a fragment shader distributor, a fragment shader collector, and a plurality of fragment shader pipelines. Each fragment shader pipeline executes a fragment shader program on a segment of fragments. The plurality of fragment shader pipelines operate in parallel, executing the same or different fragment shader programs. The fragment shader distributor receives a stream of fragments from a rasterization unit and dispatches a portion of the stream of fragments to a selected fragment shader pipeline until the capacity of the selected fragment shader pipeline is reached. The fragment shader distributor then selects another fragment shader pipeline. The capacity of each of the fragment shader pipelines is limited by several different resources. As the fragment shader distributor dispatches fragments, it tracks the remaining available resources of the selected fragment shader pipeline. A fragment shader collector retrieves processed fragments from the plurality of fragment shader pipelines.
摘要翻译：片段处理器包括片段着色器分配器，片段着色器收集器和多个片段着色器管线。每个片段着色器流水线在片段片段上执行片段着色器程序。多个片段着色器管线并行操作，执行相同或不同的片段着色程序。片段着色器分配器从光栅化单元接收片段流，并将片段流的一部分分派到所选择的片段着色器管线，直到达到所选片段着色器管线的容量。片段着色器分配器然后选择另一个片段着色器管道。每个片段着色器管道的容量受到几个不同的资源的限制。当片段着色器分配器调度片段时，它会跟踪所选片段着色器管道的剩余可用资源。片段着色器收集器从多个片段着色器管道中检索已处理的片段。

7. 发明授权

US07884831B2 Reconfigurable high-performance texture pipeline with advanced filtering 有权
标题翻译：可重构高性能纹理管道，具有先进的过滤功能
公开(公告)号：US07884831B2
公开(公告)日：2011-02-08
申请号：US12689939
申请日：2010-01-19
申请人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J. M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
发明人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J. M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
IPC分类号： G06T17/00 , G06T11/40 , G09G5/00 , G09G5/02 , G06K9/40 , G06K9/32 , G06K9/64
CPC分类号： G06T1/60 , G06F3/14 , G06T15/04 , G06T2200/28 , G09G5/026 , G09G5/22 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以快速和有效的方式存储和检索纹素。一个这样的纹理电路为一组像素中的每个像素提供了更多数量的iler骨，特别是当需要三线性或茴香过滤时。对于三线性滤波，在一个时钟周期内针对多个像素检索第一和第二细节级别的纹素。当执行了茴香过滤时，可以在一个时钟周期内为多个像素中的每一个检索多个b骨。

8. 发明授权

US07649538B1 Reconfigurable high performance texture pipeline with advanced filtering 有权
标题翻译：可重构的高性能纹理管道与先进的过滤
公开(公告)号：US07649538B1
公开(公告)日：2010-01-19
申请号：US11556674
申请日：2006-11-03
申请人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J. M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donovan , Emmett M. Kilgariff
发明人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J. M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donovan , Emmett M. Kilgariff
IPC分类号： G06T17/00 , G06T11/40 , G09G5/00 , G09G5/02 , G06K9/40 , G06K9/32 , G06K9/64
CPC分类号： G06T1/60 , G06F3/14 , G06T15/04 , G06T2200/28 , G09G5/026 , G09G5/22 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以快速和有效的方式存储和检索纹素。一个这样的纹理电路为一组像素中的每个像素提供了更多数量的iler骨，特别是当需要三线性或茴香过滤时。对于三线性滤波，在一个时钟周期内针对多个像素检索第一和第二细节级别的纹素。当执行了茴香过滤时，可以在一个时钟周期内为多个像素中的每一个检索多个b骨。

9. 发明申请

US20070008336A1 PIXEL CENTER POSITION DISPLACEMENT 有权
标题翻译：像素中心位置位移
公开(公告)号：US20070008336A1
公开(公告)日：2007-01-11
申请号：US11532069
申请日：2006-09-14
申请人： Rui Bastos , Michael Toksvig , Karim Abdalla
发明人： Rui Bastos , Michael Toksvig , Karim Abdalla
IPC分类号： G09G5/00
CPC分类号： G06T3/40
摘要： A pixel center position that is not covered by a primitive covering a portion of the pixel is displaced to lie within a fragment formed by the intersection of the primitive and the pixel. X,y coordinates of a pixel center are adjusted to displace the pixel center position to lie within the fragment, affecting actual texture map coordinates or barycentric weights. Alternatively, a centroid sub-pixel sample position is determined based on coverage data for the pixel and a multisample mode. The centroid sub-pixel sample position is used to compute pixel or sub-pixel parameters for the fragment.
摘要翻译：未被覆盖像素的一部分的原图覆盖的像素中心位置被移位以位于由图元和像素的交点形成的片段内。调整像素中心的X，Y坐标以使像素中心位置位于片段内，影响实际纹理图坐标或重心权重。或者，基于像素的覆盖数据和多采样模式来确定质心子像素采样位置。质心子像素采样位置用于计算片段的像素或子像素参数。

10. 发明申请

US20060077209A1 Pixel center position displacement 有权
公开(公告)号：US20060077209A1
公开(公告)日：2006-04-13
申请号：US10960857
申请日：2004-10-07
申请人： Rui Bastos , Michael Toksvig , Karim Abdalla
发明人： Rui Bastos , Michael Toksvig , Karim Abdalla
IPC分类号： G09G5/00
CPC分类号： G06T3/40
摘要： A pixel center position that is not covered by a primitive covering a portion of the pixel is displaced to lie within a fragment formed by the intersection of the primitive and the pixel. X,y coordinates of a pixel center are adjusted to displace the pixel center position to lie within the fragment, affecting actual texture map coordinates or barycentric weights. Alternatively, a centroid sub-pixel sample position is determined based on coverage data for the pixel and a multisample mode. The centroid sub-pixel sample position is used to compute pixel or sub-pixel parameters for the fragment.

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