专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08300477B2 Piecewise erasure of flash memory 有权
标题翻译：分片擦除闪存
公开(公告)号：US08300477B2
公开(公告)日：2012-10-30
申请号：US12920564
申请日：2009-02-19
申请人： Brent S. Haukness , Ian Shaeffer , Gary B. Bronner
发明人： Brent S. Haukness , Ian Shaeffer , Gary B. Bronner
IPC分类号： G11C11/34 , G11C16/04 , G11C7/00 , G11C8/00
CPC分类号： G11C16/16
摘要： Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multiple piecewise-erase commands within the memory device may be insufficient to erase the information stored in the storage cell. Moreover, the first circuit includes an interface that receives the multiple piecewise-erase commands from the control logic and that transmits the multiple piecewise-erase commands to the memory device.
摘要翻译：描述电路的实施例。该电路包括产生多个分段擦除命令的控制逻辑，以擦除存储在另一个电路内形成的存储器件的存储单元中的信息。注意，在存储器件内执行多个分段擦除命令中的单个擦除命令可能不足以擦除存储在存储单元中的信息。此外，第一电路包括从控制逻辑接收多个分段擦除命令并将多个分段擦除命令发送到存储器件的接口。

2. 发明授权

US09966142B2 Fractional program commands for memory devices 有权
公开(公告)号：US09966142B2
公开(公告)日：2018-05-08
申请号：US12990945
申请日：2009-05-06
申请人： Brent S. Haukness , Ian Shaeffer , Gary B. Bronner
发明人： Brent S. Haukness , Ian Shaeffer , Gary B. Bronner
IPC分类号： G06F12/00 , G11C16/10 , G06F3/06
CPC分类号： G11C16/10 , G06F3/0611 , G06F3/0659 , G06F3/0688
摘要： A memory system (100B) includes an array of non-volatile memory cells (140) and a memory controller (110) having a first port (port connected to line 101) to receive a program command that addresses a number of the memory cells for a programming operation, having a second port (port connected to lines 102 and 103) coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.

3. 发明申请

US20110060875A1 FRACTIONAL PROGRAM COMMANDS FOR MEMORY DEVICES 审中-公开
标题翻译：内存设备的部分程序命令
公开(公告)号：US20110060875A1
公开(公告)日：2011-03-10
申请号：US12990945
申请日：2009-05-06
申请人： Brent S. Haukness , Ian Shaeffer , Gary B. Bronner
发明人： Brent S. Haukness , Ian Shaeffer , Gary B. Bronner
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C16/10 , G06F3/0611 , G06F3/0659 , G06F3/0688
摘要： A memory system (100B) includes an array of non-volatile memory cells (140) and a memory controller (110) having a first port (port connected to line 101) to receive a program command that addresses a number of the memory cells for a programming operation, having a second port (port connected to lines 102 and 103) coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.
摘要翻译：存储器系统（100B）包括非易失性存储单元阵列（140）和存储器控制器（110），存储器控制器（110）具有第一端口（连接到线101的端口），以接收编址命令，编程操作，具有经由命令流水线耦合到存储器阵列的第二端口（连接到线102和103的端口），并且被配置为响应于程序命令创建多个分数程序命令。每个分数程序命令的执行将单个程序脉冲施加到所寻址的存储器单元，以使用程序数据递增地编程所寻址的存储器单元，其中与每个分数程序命令相关联的编程脉冲的持续时间通常为总编程时间的选定分数需要对存储单元进行编程。

4. 发明申请

US20110004726A1 PIECEWISE ERASURE OF FLASH MEMORY 有权
标题翻译：闪存存储器的擦除
公开(公告)号：US20110004726A1
公开(公告)日：2011-01-06
申请号：US12920564
申请日：2009-02-19
申请人： Brent S. Haukness , Ian Shaeffer , Gary B. Bronner
发明人： Brent S. Haukness , Ian Shaeffer , Gary B. Bronner
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C16/16
摘要： Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multiple piecewise-erase commands within the memory device may be insufficient to erase the information stored in the storage cell. Moreover, the first circuit includes an interface that receives the multiple piecewise-erase commands from the control logic and that transmits the multiple piecewise-erase commands to the memory device.
摘要翻译：描述电路的实施例。该电路包括产生多个分段擦除命令的控制逻辑，以擦除存储在另一个电路内形成的存储器件的存储单元中的信息。注意，在存储器件内执行多个分段擦除命令中的单个擦除命令可能不足以擦除存储在存储单元中的信息。此外，第一电路包括从控制逻辑接收多个分段擦除命令并将多个分段擦除命令发送到存储器件的接口。

5. 发明授权

US08344475B2 Integrated circuit heating to effect in-situ annealing 有权
标题翻译：集成电路加热实现原位退火
公开(公告)号：US08344475B2
公开(公告)日：2013-01-01
申请号：US12859554
申请日：2010-08-19
申请人： Ian P. Shaeffer , Gary B. Bronner , Brent S. Haukness , Kevin S. Donnelly , Frederick A. Ware , Mark A. Horowitz
发明人： Ian P. Shaeffer , Gary B. Bronner , Brent S. Haukness , Kevin S. Donnelly , Frederick A. Ware , Mark A. Horowitz
IPC分类号： H01L29/00
CPC分类号： G11C16/26 , G11C7/04 , G11C13/0002 , G11C13/0033 , G11C13/0035 , G11C16/06 , H01L21/324
摘要： In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.
摘要翻译：在具有存储器件的系统中，在系统操作期间检测到事件。响应于检测到事件，存储器件被加热以反转存储器件的使用中的劣化。在另一系统中，存储器件被加热以与系统的另一个存储器件内的数据访问操作的执行同时反向使用所引起的降级。在具有耦合到第一和第二存储器设备的存储器控制器的另一系统中，响应于确定在第一存储器设备内需要维护操作，将数据从第一存储器设备抽出到第二存储器设备。

6. 发明申请

US20110299317A1 INTEGRATED CIRCUIT HEATING TO EFFECT IN-SITU ANNEALING 有权
标题翻译：集成电路加热来影响现场退火
公开(公告)号：US20110299317A1
公开(公告)日：2011-12-08
申请号：US12859554
申请日：2010-08-19
申请人： Ian P. Shaeffer , Gary B. Bronner , Brent S. Haukness , Kevin S. Donnelly , Frederick A. Ware , Mark A. Horowitz
发明人： Ian P. Shaeffer , Gary B. Bronner , Brent S. Haukness , Kevin S. Donnelly , Frederick A. Ware , Mark A. Horowitz
IPC分类号： G11C13/00 , H01L21/26
CPC分类号： G11C16/26 , G11C7/04 , G11C13/0002 , G11C13/0033 , G11C13/0035 , G11C16/06 , H01L21/324
摘要： In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.
摘要翻译：在具有存储器件的系统中，在系统操作期间检测到事件。响应于检测到事件，存储器件被加热以反转存储器件的使用中的劣化。在另一系统中，存储器件被加热以与系统的另一个存储器件内的数据访问操作的执行同时反向使用所引起的降级。在具有耦合到第一和第二存储器设备的存储器控制器的另一系统中，响应于确定在第一存储器设备内需要维护操作，将数据从第一存储器设备撤出到第二存储器设备。

7. 发明授权

US08310872B2 Multi-page parallel program flash memory 有权
标题翻译：多页并行程序闪存
公开(公告)号：US08310872B2
公开(公告)日：2012-11-13
申请号：US12863409
申请日：2009-01-16
申请人： Yoshihito Koya , Gary B. Bronner , Frederick A. Ware
发明人： Yoshihito Koya , Gary B. Bronner , Frederick A. Ware
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/24
摘要： A NAND flash memory device having a bit line and a plurality of storage cells coupled thereto. Programming circuitry is coupled to the plurality of storage cells concurrently to program two or more of the storage cells in different NAND strings associated with the same bit line.
摘要翻译：具有位线和与其耦合的多个存储单元的NAND快闪存储器件。编程电路同时耦合到多个存储单元，以对与相同位线相关联的不同NAND串中的两个或更多个存储单元进行编程。

8. 发明申请

US20120236668A1 MEMORY MODULE WITH DISCRETE HEATING ELEMENT 失效
标题翻译：带离散加热元件的记忆模块
公开(公告)号：US20120236668A1
公开(公告)日：2012-09-20
申请号：US13486977
申请日：2012-06-01
申请人： Gary B. Bronner , Ming Li , Donald R. Mullen , Frederick Ware , Kevin S. Donnelly
发明人： Gary B. Bronner , Ming Li , Donald R. Mullen , Frederick Ware , Kevin S. Donnelly
IPC分类号： G11C29/00 , H01L27/08
CPC分类号： G11C16/349 , G11C16/3418 , H01L23/3128 , H01L23/345 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/06589 , H01L2924/15311 , H01L2924/19107 , H01L2924/00012 , H01L2924/00
摘要： A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The discrete heating elements, or single discrete heating element, heats the memory devices to a temperature that anneals the defects.
摘要翻译：存储器模块包括安装到基板的多个存储器件和与存储器件热接触地设置的一个或多个分立加热元件。每个存储器件包括经受操作引起的缺陷的电荷存储存储单元，其使存储器单元存储数据的能力降低。离散加热元件或单独的分立加热元件将存储器件加热到退火缺陷的温度。

9. 发明授权

US07009237B2 Out of the box vertical transistor for eDRAM on SOI 有权
标题翻译：在SOI上用于eDRAM的开箱式垂直晶体管
公开(公告)号：US07009237B2
公开(公告)日：2006-03-07
申请号：US10709450
申请日：2004-05-06
申请人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
发明人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.
摘要翻译：本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件掩埋氧化层。上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。

10. 发明授权

US06566177B1 Silicon-on-insulator vertical array device trench capacitor DRAM 有权
标题翻译：绝缘体上的垂直阵列器件沟槽电容器DRAM
公开(公告)号：US06566177B1
公开(公告)日：2003-05-20
申请号：US09427257
申请日：1999-10-25
申请人： Carl J. Radens , Gary B. Bronner , Tze-chiang Chen , Bijan Davari , Jack A. Mandelman , Dan Moy , Devendra K. Sadana , Ghavam Ghavami Shahidi , Scott R. Stiffler
发明人： Carl J. Radens , Gary B. Bronner , Tze-chiang Chen , Bijan Davari , Jack A. Mandelman , Dan Moy , Devendra K. Sadana , Ghavam Ghavami Shahidi , Scott R. Stiffler
IPC分类号： H01L2100
CPC分类号： H01L27/10864 , H01L27/1087
摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench. A polysilicon capacitor plate is formed in the deep trenches and conductive polysilicon straps are formed in the trenches between the capacitor plates and the SOI sidewalls. Device regions are defined in the wafer and a sidewall gate is formed in the deep trenches. Shallow trenches isolation (STI) is used to isolate and define cells. Bitlines and wordlines are formed on the wafer.
摘要翻译：一种绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元及阵列及其制造方法。存储单元包括通过自对准埋入带连接到垂直存取晶体管的沟槽存储电容器。掩埋氧化层将SOI层与硅衬底隔离。沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。连接到存储电容器的多晶硅板的多晶硅带提供与存取晶体管的源极的自对准接触。最初，在晶圆中形成掩埋氧化物层。深沟槽被蚀刻，最初刚刚通过SOI层和BOX层。在沟槽中形成保护侧壁。然后，将深沟槽蚀刻到衬底中。衬底中的体积被扩大以形成瓶形沟槽。在深沟槽中形成多晶硅电容器板，并且在电容器板和SOI侧壁之间的沟槽中形成导电多晶硅带。在晶片中限定器件区域，并且在深沟槽中形成侧壁栅极。浅沟槽隔离（STI）用于隔离和定义细胞。在晶片上形成位线和字线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式