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1. 发明授权

US5329621A Microprocessor which optimizes bus utilization based upon bus speed 失效
标题翻译：基于总线速度优化总线利用率的微处理器
公开(公告)号：US5329621A
公开(公告)日：1994-07-12
申请号：US425082
申请日：1989-10-23
申请人： Bradley G. Burgess , James B. Eifert , Michael S. Taborn
发明人： Bradley G. Burgess , James B. Eifert , Michael S. Taborn
IPC分类号： G06F9/38 , G06F9/28
CPC分类号： G06F9/3804
摘要： A data processing apparatus having a bus speed counter for determining the bus speed of a previous bus cycle. This previous bus speed information is then used to optimize bus utilization. This bus speed information is particularly useful for determining whether to run prefetch bus cycles during the execution of a conditional branch instruction. If previous bus cycles have been slow, prefetch procrastination can occurs until the branch condition resolves.
摘要翻译：一种具有用于确定先前总线周期的总线速度的总线速度计数器的数据处理装置。然后使用以前的总线速度信息来优化总线利用率。该总线速度信息对于在执行条件转移指令期间确定是否运行预取总线周期特别有用。如果以前的总线周期一直很慢，则可能会发生预取拖延，直到分支条件解决。

2. 发明授权

US5448744A Integrated circuit microprocessor with programmable chip select logic 失效
标题翻译：具有可编程芯片选择逻辑的集成电路微处理器
公开(公告)号：US5448744A
公开(公告)日：1995-09-05
申请号：US432423
申请日：1989-11-06
申请人： James B. Eifert , John J. Vaglica , James C. Smallwood , Mark W. McDermott , Hiroyuki Sugiyama , William P. LaViolette , Bradley G. Burgess
发明人： James B. Eifert , John J. Vaglica , James C. Smallwood , Mark W. McDermott , Hiroyuki Sugiyama , William P. LaViolette , Bradley G. Burgess
IPC分类号： G06F9/38 , G06F9/22 , G06F13/10
CPC分类号： G06F9/3877
摘要： An integrated circuit microprocessor has on-board programmable chip select logic. Each of several chip select outputs is individually programmable by means of one or more control register bit fields. For instance, each chip select is asserted for bus cycles within an address range whose starting address and block size are both programmable. In addition, each chip select can be programmed to be active on read cycles only, on write cycles only, or on both read and write cycles. Each chip select can be programmed to be active during interrupt acknowledge cycles only if the interrupt being acknowledged has the same priority level as has been programmed for that chip select. In addition, the timing of the assertion of each chip select is programmable to coincide with either the address strobe or data strobe of the bus cycle. The chip select logic is designed so that it is configured to come out of reset by producing an active chip select signal during the first bus cycle run by the processor following the reset. This chip select is appropriate for selecting a boot ROM, and may later be re-programmed for other use. The chip select logic is capable of supporting cycle-by-cycle dynamic bus sizing by asserting appropriate cycle termination signals. The chip select logic can also insert a programmable number of wait states into a bus cycle to accommodate slow peripherals or can cause a fast termination of a bus cycle to improve the utilization of fast peripherals.
摘要翻译：集成电路微处理器具有板载可编程芯片选择逻辑。几个芯片选择输出中的每一个可以通过一个或多个控制寄存器位字段单独编程。例如，每个芯片选择在起始地址和块大小均可编程的地址范围内被断言用于总线周期。此外，每个芯片选择都可以被编程为仅在读周期有效，仅在写周期或读周期和写周期。只有在确认中断与该芯片选择相同的优先级时，每个芯片选择才能在中断确认周期内被编程为有效。此外，每个芯片选择的断言的定时可编程为与总线周期的地址选通或数据选通一致。芯片选择逻辑被设计为使得其被配置为在复位之后由处理器运行的第一总线周期期间产生有效芯片选择信号而退出复位。该芯片选择适用于选择引导ROM，然后可以重新编程以供其他使用。芯片选择逻辑能够通过断言适当的周期终止信号来支持逐周期动态总线大小调整。芯片选择逻辑还可以将可编程的等待状态数插入总线周期以适应慢速外设，或者可能导致总线周期的快速终止，从而提高快速外设的利用率。

3. 发明授权

US5072365A Direct memory access controller using prioritized interrupts for varying bus mastership 失效
标题翻译：直接存储器访问控制器使用优化中断来改变总线主控
公开(公告)号：US5072365A
公开(公告)日：1991-12-10
申请号：US457647
申请日：1989-12-27
申请人： Bradley G. Burgess , James B. Eifert , John P. Dunn
发明人： Bradley G. Burgess , James B. Eifert , John P. Dunn
IPC分类号： G06F13/28 , G06F13/34
CPC分类号： G06F13/34
摘要： A data processing system having a direct memory access controller (DMAC) which can be interrupted with a prioritized signal to vary bus mastership of a communication bus in the system. A prioritized interrupt signal is sent to a CPU when the DMAC has bus mastership. The CPU only informs the DMAC of the highest priority cumulative interrupt priority. With the use of a mask value, the interrupt may be selectively screened by the DMAC so that selective interrupts may remove bus mastership from the DMAC.

4. 发明授权

US07809980B2 Error detector in a cache memory using configurable way redundancy 有权
标题翻译：使用可配置方式冗余的缓存中的错误检测器
公开(公告)号：US07809980B2
公开(公告)日：2010-10-05
申请号：US11951924
申请日：2007-12-06
申请人： Jehoda Refaeli , Florian Bogenberger , James B. Eifert
发明人： Jehoda Refaeli , Florian Bogenberger , James B. Eifert
IPC分类号： G06F11/00
CPC分类号： G06F11/1064 , G06F12/0864 , G06F12/126 , G06F2212/601
摘要： A data processing system includes a processor having a multi-way cache which has a first and a second way. The second way is configurable to either be redundant to the first way or to operate as an associative way independent of the first way. The system may further include a memory, where the processor, in response to a read address missing in the cache, provides the read address to the memory. The second way may be dynamically configured to be redundant to the first way during operation of the processor in response to an error detection signal. In one aspect, when the second way is configured to be redundant, in response to the read address hitting in the cache, data addressed by an index portion of the read address is provided from both the first and second way and compared to each other to determine if a comparison error exists.
摘要翻译：数据处理系统包括具有第一和第二方式的多路缓存的处理器。第二种方式是配置为第一种方式是冗余的，或作为独立于第一种方式的关联方式运行。系统还可以包括存储器，其中响应于高速缓存中缺少的读取地址的处理器将读取地址提供给存储器。响应于错误检测信号，在处理器的操作期间，第二种方式可被动态配置为在第一种方式中是冗余的。在一个方面，当第二种方式被配置为冗余时，响应于高速缓存中的读取地址，由读取地址的索引部分寻址的数据从第一和第二方式提供并相互比较确定是否存在比较错误。

5. 发明授权

US06240493B1 Method and apparatus for performing access censorship in a data processing system 失效
标题翻译：用于在数据处理系统中执行访问审查的方法和装置
公开(公告)号：US06240493B1
公开(公告)日：2001-05-29
申请号：US09061974
申请日：1998-04-17
申请人： Wallace B. Hardwood, III , James B. Eifert , Thomas R. Toms
发明人： Wallace B. Hardwood, III , James B. Eifert , Thomas R. Toms
IPC分类号： G06F1214
CPC分类号： G06F21/71 , G06F21/62
摘要： Method and apparatus for performing access censorship in a data processing system (10). In one embodiment, a digital data processing system (10) has a sub-system (34) that can be protected against intrusions, yet is still accessible and/or alterable under certain defined conditions. In a non-volatile storage portion (48) of the data processing system (10), censorship information is stored to enable an access control mechanism. Access control information (42) to selectively disable the access control mechanism is programmably generated. Additional access control information (44) can be employed to reprogram a data processing system (10) containing access protected data in a secure mode.
摘要翻译：用于在数据处理系统（10）中执行访问审查的方法和装置。在一个实施例中，数字数据处理系统（10）具有子系统（34），其可以被保护免受入侵，但是在某些限定的条件下仍可访问和/或可变。在数据处理系统（10）的非易失性存储部分（48）中，存储检查信息以实现访问控制机制。可编程地产生用于选择性地禁用访问控制机制的访问控制信息（42）。可以采用额外的访问控制信息（44）来重新编程包含安全模式的访问保护数据的数据处理系统（10）。

6. 发明授权

US5727172A Method and apparatus for performing atomic accesses in a data processing system 失效
标题翻译：用于在数据处理系统中执行原子访问的方法和装置
公开(公告)号：US5727172A
公开(公告)日：1998-03-10
申请号：US431943
申请日：1995-05-01
申请人： James B. Eifert , Adi Sapir , Wallace B. Harwood, III
发明人： James B. Eifert , Adi Sapir , Wallace B. Harwood, III
IPC分类号： G06F13/36 , G06F13/40 , G06F13/14
CPC分类号： G06F13/4036 , G06F13/36
摘要： A method and apparatus for performing atomic accesses in a data processing system (10). In one embodiment, a small number of control signals (e.g. 100-102; or 103-104; or 105-108 from FIG. 3 ) are used to provide information regarding the status of reservations between bus masters (e.g. 80), bus interfaces (e.g. 84, 86, and 92), and snoop logic (e.g. 82,88, and 90). Snoop logic (e.g. 40 in FIG. 2) is required if multiple bus masters (12 and 46) are used. The control signals allow atomic accesses to be performed in a multi-master data processing system (10), while minimizing the circuitry required to be built on-board each bus master integrated circuit processor (e.g. 152 in FIG. 3). The result is lower cost processors (152) which can operate in multi-processor systems, but which are optimized for use in single-processor systems.
摘要翻译：一种用于在数据处理系统（10）中执行原子访问的方法和装置。在一个实施例中，使用少量控制信号（例如，图10中的100-102;或103-104;或105-108）来提供关于总线主控（例如80），总线接口（例如84,86和92）和窥探逻辑（例如82,88和90）。如果使用多个总线主机（12和46），则需要侦听逻辑（如图2中的40）。控制信号允许在多主数据处理系统（10）中执行原子访问，同时使需要构建在板上的每个总线主集成电路处理器（例如图3中的152）所需的电路最小化。其结果是可以在多处理器系统中运行的成本较低的处理器（152），但是它们被优化用于单处理器系统。

7. 发明授权

US5675749A Method and apparatus for controlling show cycles in a data processing system 失效
标题翻译：用于控制数据处理系统中的显示周期的方法和装置
公开(公告)号：US5675749A
公开(公告)日：1997-10-07
申请号：US460484
申请日：1995-06-02
申请人： Jay A. Hartvigsen , James B. Eifert , Wallace B. Harwood, III , Jeffrey A. Hopkins
发明人： Jay A. Hartvigsen , James B. Eifert , Wallace B. Harwood, III , Jeffrey A. Hopkins
IPC分类号： G06F11/34 , G06F11/36 , G06F9/00
CPC分类号： G06F11/3648 , G06F11/349
摘要： The present invention relates in general to a data processing system (10), and more particularly to a method and apparatus for controlling showcycles in a data processing system (10) to provide user control over the tradeoff between internal bus visibility and operating performance. In one embodiment, the functionality of one or more register control bits (100, 102) can be combined with the functionality of one or more externally provided signals (78) to allow the user to have a wide range of control over the show cycles provided on external bus 12. The user is thus able to continuously select and change which information is provided by way of show cycles on external bus 12. As a result, the difficulty of debugging software program code can potentially be reduced.
摘要翻译：本发明一般涉及一种数据处理系统（10），更具体地涉及一种用于控制数据处理系统（10）中的显示的方法和装置，以提供用户对内部总线可见性和操作性能之间权衡的控制。在一个实施例中，一个或多个寄存器控制位（100,102）的功能可以与一个或多个外部提供的信号（78）的功能组合，以允许用户对所提供的显示循环进行宽范围的控制因此，用户能够连续地选择和改变通过外部总线12上的显示周期来提供哪些信息。结果，可以有可能降低调试软件程序代码的难度。

8. 发明申请

US20110167198A1 NON-VOLATILE STORAGE ALTERATION TRACKING 有权
标题翻译：非易失性存储变换跟踪
公开(公告)号：US20110167198A1
公开(公告)日：2011-07-07
申请号：US12683549
申请日：2010-01-07
申请人： Richard Soja , James B. Eifert , Timothy J. Strauss
发明人： Richard Soja , James B. Eifert , Timothy J. Strauss
IPC分类号： G06F12/02
CPC分类号： G06F12/1425
摘要： A method for tracking alteration of a non-volatile storage includes receiving a request to modify a tracked region of the non-volatile storage. In response to the request, it is determined whether or not a modification of data stored in a non-erasable one-time programmable (NEOTP) alteration log region has occurred. In response to determining that the modification of the data stored in the NEOTP alteration log region has occurred, the tracked region of non-volatile storage is modified in response to the request. In response to determining that the modification of the data stored in the NEOTP alteration log region has not occurred, the request to modify the tracked region of the non-volatile memory is denied.
摘要翻译：用于跟踪非易失性存储器的改变的方法包括接收修改非易失性存储器的被跟踪区域的请求。响应于该请求，确定是否发生存储在不可擦除的一次性可编程（NEOTP）改变对数区域中的数据的修改。响应于确定存储在NEOTP改变日志区域中的数据的修改已经发生，响应于该请求来修改非易失性存储的跟踪区域。响应于确定没有发生存储在NEOTP改变日志区域中的数据的修改，修改非易失性存储器的跟踪区域的请求被拒绝。

9. 发明授权

US6079015A Data processing system having selectable exception table relocation and method therefor 失效
标题翻译：具有可选异常表重定位的数据处理系统及其方法
公开(公告)号：US6079015A
公开(公告)日：2000-06-20
申请号：US62952
申请日：1998-04-20
申请人： Wallace B. Harwood, III , James B. Eifert , Rami Natan , Yossi Asher , Avi Ginsberg
发明人： Wallace B. Harwood, III , James B. Eifert , Rami Natan , Yossi Asher , Avi Ginsberg
IPC分类号： G06F9/48 , G06F12/02
CPC分类号： G06F9/4812 , G06F9/3861
摘要： A data processing system (20) has a central processing unit (CPU) (22) and a memory (30) for storing an exception table. The exception table is mapped in the memory (30) in consecutive segments, with each segment for storing a predetermined number of instructions for executing the exception. By asserting a control bit, the exception table can be relocated, or remapped, and compressed into a jump table. The jump table stores only jump instruction for branching to the exception routines, which are relocated to other memory locations. The jump table is generated from the starting addresses of the exception routines. Relocating the exception routines allows for more efficient use of internal memory space of the data processing system (20).
摘要翻译：数据处理系统（20）具有中央处理单元（CPU）（22）和用于存储异常表的存储器（30）。异常表以连续的段映射到存储器（30）中，每个段用于存储用于执行异常的预定数量的指令。通过断言控制位，异常表可以重新定位或重新映射，并被压缩成跳转表。跳转表仅存储用于分支到异常例程的跳转指令，这些例程被重新定位到其他内存位置。跳转表是从异常例程的起始地址生成的。重新定位异常例程允许更有效地使用数据处理系统（20）的内部存储器空间。

10. 发明授权

US5717931A Method and apparatus for communicating between master and slave electronic devices where the slave device may be hazardous 失效
标题翻译：主从电子设备之间进行通信的方法和装置，其中从设备可能是危险的
公开(公告)号：US5717931A
公开(公告)日：1998-02-10
申请号：US359969
申请日：1994-12-20
申请人： Adi Sapir , Ilan Pardo , James B. Eifert , Wallace B. Harwood, III , John J. Vaglica , Danny Shterman
发明人： Adi Sapir , Ilan Pardo , James B. Eifert , Wallace B. Harwood, III , John J. Vaglica , Danny Shterman
IPC分类号： G06F9/38 , G06F11/28 , G06F13/16 , G06F9/40
CPC分类号： G06F13/1605
摘要： A master device (11) can access slave devices (12) either speculatively or non-speculatively. The slave devices (12) can be either non-hazardous devices or hazardous devices which exhibit status changes on reading. The master device (11) issues an access request including information as to whether the request is speculative or non-speculative, the slave device (12) then responds to the master device (11) with a negative acknowledgment that access is denied if the access request is speculative and the slave device (12) is hazardous. Otherwise, if the slave device (12) can deal with the request, a positive acknowledgment is sent. If the master device (11) receives a negative acknowledgment, it continues to reissue updated access requests until a positive acknowledgment is received.
摘要翻译：主设备（11）可以以推测或非推测方式访问从设备（12）。从设备（12）可以是非危险设备或在读取时显示状态变化的危险设备。主设备（11）发布包括关于请求是否是推测性的信息的访问请求，从设备（12）随后以否定确认来响应主设备（11），如果访问被拒绝则访问被拒绝请求是推测性的，从设备（12）是危险的。否则，如果从设备（12）可以处理请求，则发送肯定确认。如果主设备（11）接收到否定确认，则继续重新发送更新的接入请求，直到收到肯定确认。

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