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    • 2. 发明授权
    • Method and apparatus for performing atomic accesses in a data processing
system
    • 用于在数据处理系统中执行原子访问的方法和装置
    • US5727172A
    • 1998-03-10
    • US431943
    • 1995-05-01
    • James B. EifertAdi SapirWallace B. Harwood, III
    • James B. EifertAdi SapirWallace B. Harwood, III
    • G06F13/36G06F13/40G06F13/14
    • G06F13/4036G06F13/36
    • A method and apparatus for performing atomic accesses in a data processing system (10). In one embodiment, a small number of control signals (e.g. 100-102; or 103-104; or 105-108 from FIG. 3 ) are used to provide information regarding the status of reservations between bus masters (e.g. 80), bus interfaces (e.g. 84, 86, and 92), and snoop logic (e.g. 82,88, and 90). Snoop logic (e.g. 40 in FIG. 2) is required if multiple bus masters (12 and 46) are used. The control signals allow atomic accesses to be performed in a multi-master data processing system (10), while minimizing the circuitry required to be built on-board each bus master integrated circuit processor (e.g. 152 in FIG. 3). The result is lower cost processors (152) which can operate in multi-processor systems, but which are optimized for use in single-processor systems.
    • 一种用于在数据处理系统(10)中执行原子访问的方法和装置。 在一个实施例中,使用少量控制信号(例如,图10中的100-102;或103-104;或105-108)来提供关于总线主控(例如80),总线接口 (例如84,86和92)和窥探逻辑(例如82,88和90)。 如果使用多个总线主机(12和46),则需要侦听逻辑(如图2中的40)。 控制信号允许在多主数据处理系统(10)中执行原子访问,同时使需要构建在板上的每个总线主集成电路处理器(例如图3中的152)所需的电路最小化。 其结果是可以在多处理器系统中运行的成本较低的处理器(152),但是它们被优化用于单处理器系统。
    • 3. 发明授权
    • Method and apparatus for implementing a in-order termination bus
protocol within a data processing system
    • 用于在数据处理系统内实现按顺序终端总线协议的方法和装置
    • US5699516A
    • 1997-12-16
    • US363435
    • 1994-12-22
    • Adi SapirJames B. Eifert
    • Adi SapirJames B. Eifert
    • G06F13/36
    • G06F13/36
    • A bus protocol is provided for pipelined and/or split transaction buses (18,48) which have in-order data bus termination and which do not require data bus arbitration. The present invention solves the problem of matching the initial address request by a bus master (12, 13, 42) to the corresponding data response from a bus slave (14, 15, 44) when the bus (18, 48) used for master-slave communication is a split-transaction bus and/or a pipelined bus. Each bus master (12, 13, 42) and each bus slave (14, 15, 44) has a counter (30-33, 75-76) which is used to store a current pipe depth value (21, 51) from a central pipe counter (16, 72). A transaction start signal (20, 50) and a transaction end signal (22, 52) are used to selectively increment and decrement the counters (30-33, 75-76).
    • 为流水线和/或分离事务总线(18,48)提供总线协议,这些总线协议具有按顺序数据总线终止并且不需要数据总线仲裁。 本发明解决了当用于主机的总线(18,48)时,总线主机(12,13,42)将初始地址请求与来自总线从机(14,15,44)的相应数据响应匹配的问题 -slave通信是分组交易总线和/或流水线总线。 每个总线主控器(12,13,42)和每个总线从机(14,15,44)具有一个计数器(30-33,75-76),用于存储当前管道深度值(21,51) 中央管道计数器(16,72)。 交易开始信号(20,50)和交易结束信号(22,52)用于选择性地递增和递减计数器(30-33,75-76)。