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1. 发明申请

US20110167198A1 NON-VOLATILE STORAGE ALTERATION TRACKING 有权
标题翻译：非易失性存储变换跟踪
公开(公告)号：US20110167198A1
公开(公告)日：2011-07-07
申请号：US12683549
申请日：2010-01-07
申请人： Richard Soja , James B. Eifert , Timothy J. Strauss
发明人： Richard Soja , James B. Eifert , Timothy J. Strauss
IPC分类号： G06F12/02
CPC分类号： G06F12/1425
摘要： A method for tracking alteration of a non-volatile storage includes receiving a request to modify a tracked region of the non-volatile storage. In response to the request, it is determined whether or not a modification of data stored in a non-erasable one-time programmable (NEOTP) alteration log region has occurred. In response to determining that the modification of the data stored in the NEOTP alteration log region has occurred, the tracked region of non-volatile storage is modified in response to the request. In response to determining that the modification of the data stored in the NEOTP alteration log region has not occurred, the request to modify the tracked region of the non-volatile memory is denied.
摘要翻译：用于跟踪非易失性存储器的改变的方法包括接收修改非易失性存储器的被跟踪区域的请求。响应于该请求，确定是否发生存储在不可擦除的一次性可编程（NEOTP）改变对数区域中的数据的修改。响应于确定存储在NEOTP改变日志区域中的数据的修改已经发生，响应于该请求来修改非易失性存储的跟踪区域。响应于确定没有发生存储在NEOTP改变日志区域中的数据的修改，修改非易失性存储器的跟踪区域的请求被拒绝。

2. 发明授权

US08380918B2 Non-volatile storage alteration tracking 有权
标题翻译：非易失性存储改变跟踪
公开(公告)号：US08380918B2
公开(公告)日：2013-02-19
申请号：US12683549
申请日：2010-01-07
申请人： Richard Soja , James B. Eifert , Timothy J. Strauss
发明人： Richard Soja , James B. Eifert , Timothy J. Strauss
IPC分类号： G06F13/00
CPC分类号： G06F12/1425
摘要： A method for tracking alteration of a non-volatile storage includes receiving a request to modify a tracked region of the non-volatile storage. In response to the request, it is determined whether or not a modification of data stored in a non-erasable one-time programmable (NEOTP) alteration log region has occurred. In response to determining that the modification of the data stored in the NEOTP alteration log region has occurred, the tracked region of non-volatile storage is modified in response to the request. In response to determining that the modification of the data stored in the NEOTP alteration log region has not occurred, the request to modify the tracked region of the non-volatile memory is denied.
摘要翻译：用于跟踪非易失性存储器的改变的方法包括接收修改非易失性存储器的被跟踪区域的请求。响应于该请求，确定是否发生存储在不可擦除的一次性可编程（NEOTP）改变对数区域中的数据的修改。响应于确定存储在NEOTP改变日志区域中的数据的修改已经发生，响应于该请求来修改非易失性存储的跟踪区域。响应于确定没有发生存储在NEOTP改变日志区域中的数据的修改，修改非易失性存储器的跟踪区域的请求被拒绝。

3. 发明申请

US20070198805A1 Non-intrusive address mapping having a modified address space identifier and circuitry therefor 有权
标题翻译：非侵入式地址映射具有修改的地址空间标识符及其电路
公开(公告)号：US20070198805A1
公开(公告)日：2007-08-23
申请号：US11413430
申请日：2006-04-28
申请人： Richard Soja , William Moyer , Ray Marshall
发明人： Richard Soja , William Moyer , Ray Marshall
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0292
摘要： A method includes providing an effective address, providing an address space identifier which identifies a currently executing process, providing a mapping modifier to form a modified address space identifier where the mapping modifier is based on at least one external signal generated outside the processor, using the effective address and the modified address space identifier to form a logical address, and providing a physical address corresponding to the logical address. When the effective address has a first effective address value, the address space identifier has a first address space identifier value, and the mapping modifier has a first mapping value, the physical address has a first physical address value. When the effective address has the first effective address value, the address space identifier has the first address space identifier value, and the mapping modifier has a second mapping value, the physical address has a second physical address value.
摘要翻译：一种方法包括提供有效地址，提供标识当前执行过程的地址空间标识符，提供映射修饰符以形成修改的地址空间标识符，其中映射修饰符基于在处理器外部生成的至少一个外部信号，使用有效地址和修改的地址空间标识符以形成逻辑地址，并提供对应于逻辑地址的物理地址。当有效地址具有第一有效地址值时，地址空间标识符具有第一地址空间标识符值，并且映射修饰符具有第一映射值，物理地址具有第一物理地址值。当有效地址具有第一有效地址值时，地址空间标识符具有第一地址空间标识符值，并且映射修饰符具有第二映射值，物理地址具有第二物理地址值。

4. 发明授权

US6002992A Test system for verifying angle/time based systems and method therefor 失效
标题翻译：用于验证基于角度/时间的系统的测试系统及其方法
公开(公告)号：US6002992A
公开(公告)日：1999-12-14
申请号：US876460
申请日：1997-06-16
申请人： Mike Pauwels , Richard Soja , Chad Peckham
发明人： Mike Pauwels , Richard Soja , Chad Peckham
IPC分类号： G06F9/455 , G06F11/263 , G06F11/36
CPC分类号： G06F11/3688 , G06F11/3696
摘要： A test system (10) for testing real-time angle/time based control systems includes a digital signal generator (16), a multi-channel pulse analyzer (22), and a test system host (12). The test system host (12) controls the execution of a user generated test script. The script specifies test stimuli, external angle/time event interrupts for use by the digital signal generator (16) to a device under test (DUT) (20), and angle/time triggers used by the analyzer (22) to test the DUT (20). Using the test stimuli and external angle/time event interrupts, the DUT (20) is exercised to determine whether or not the DUT (20) and corresponding control system software operate properly. Output data from the DUT (20) are monitored by the pulse analyzer (22), which records the output data based on information specified in the script. Test results are then retrieved by the test system host (12).
摘要翻译：用于测试实时角度/时间的控制系统的测试系统（10）包括数字信号发生器（16），多通道脉冲分析仪（22）和测试系统主机（12）。测试系统主机（12）控制用户生成的测试脚本的执行。该脚本指定测试刺激，由数字信号发生器（16）用于被测设备（DUT）（20）的外部角度/时间事件中断以及分析仪（22）用于测试DUT的角度/时间触发（20）。使用测试刺激和外部角度/时间事件中断，执行DUT（20）以确定DUT（20）和相应的控制系统软件是否正常工作。来自DUT（20）的输出数据由脉冲分析器（22）监视，脉冲分析器（22）根据脚本中指定的信息来记录输出数据。然后由测试系统主机检索测试结果（12）。

5. 发明授权

US06580719B1 Method for determining the number of accesses granted during WCL and apparatus 有权
标题翻译：确定在WCL和设备期间授予的访问次数的方法
公开(公告)号：US06580719B1
公开(公告)日：2003-06-17
申请号：US09297854
申请日：1999-05-06
申请人： Marianna Soboleva , Sergej Makevev , Andrey Artamonov , Richard Soja
发明人： Marianna Soboleva , Sergej Makevev , Andrey Artamonov , Richard Soja
IPC分类号： H04L1228
CPC分类号： G06F13/362
摘要： In a method for determining a worst case service latency, first a number of accesses granted to requesting channels during the worst case service latency is determined. Therefore, the ordered list of priorities and the priority passing rules of a scheduler of the queuing system is taken into consideration so that an accurate number of access requests during the worst case service latency results. According to the number of access requests, states are selected for the different requesting channels so that the sum of the state execution times reaches a maximum according to the applicable priority passing rules. This method can be implemented by a computer program and can be advantageously used for design of an apparatus which incorporates a queuing system, such as in automobile electronics.
摘要翻译：在用于确定最坏情况的服务等待时间的方法中，首先确定在最坏情况的服务等待时间期间授予请求信道的许多访问。因此，考虑到排队系统的调度器的优先顺序列表和优先级传递规则，使得在最坏情况下的服务等待时间内的准确数量的访问请求结果。根据访问请求的数量，针对不同的请求信道选择状态，使得根据适用的优先级传递规则，状态执行时间的总和达到最大值。该方法可以通过计算机程序来实现，并且可以有利地用于设计包括诸如汽车电子设备中的排队系统的装置。

6. 发明授权

US07401201B2 Processor and method for altering address translation 有权
标题翻译：用于改变地址转换的处理器和方法
公开(公告)号：US07401201B2
公开(公告)日：2008-07-15
申请号：US11413422
申请日：2006-04-28
申请人： William C. Moyer , Ray C. Marshall , Richard Soja
发明人： William C. Moyer , Ray C. Marshall , Richard Soja
IPC分类号： G06F12/00
CPC分类号： G06F12/1027
摘要： In a processor having an address translation table, a method includes providing a logical address and control signal. When the control signal has a first value, a first physical address is provided corresponding to the logical address, and when the control signal has a second value, a second physical address is provided. The first physical address and the second physical address are stored in at least one valid entry of the address translation table. In one case, the first physical address is stored in a first valid entry having a tag field which matches the logical address and the second physical address is stored in a second valid entry having a tag field which matches the logical address. Alternatively, the first physical address is stored in a first field of a first valid entry and the second physical address is stored in a second field of the first valid entry.
摘要翻译：在具有地址转换表的处理器中，一种方法包括提供逻辑地址和控制信号。当控制信号具有第一值时，对应于逻辑地址提供第一物理地址，并且当控制信号具有第二值时，提供第二物理地址。第一物理地址和第二物理地址存储在地址转换表的至少一个有效条目中。在一种情况下，第一物理地址存储在具有与逻辑地址匹配的标签字段的第一有效条目中，并且第二物理地址被存储在具有与逻辑地址匹配的标签字段的第二有效条目中。或者，第一物理地址存储在第一有效条目的第一字段中，并且第二物理地址存储在第一有效条目的第二字段中。

7. 发明授权

US07447867B2 Non-intrusive address mapping having a modified address space identifier and circuitry therefor 有权
标题翻译：非侵入式地址映射具有修改的地址空间标识符及其电路
公开(公告)号：US07447867B2
公开(公告)日：2008-11-04
申请号：US11413430
申请日：2006-04-28
申请人： Richard Soja , William C. Moyer , Ray C. Marshall
发明人： Richard Soja , William C. Moyer , Ray C. Marshall
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0292
摘要： A method includes providing an effective address, providing an address space identifier which identifies a currently executing process, providing a mapping modifier to form a modified address space identifier where the mapping modifier is based on at least one external signal generated outside the processor, using the effective address and the modified address space identifier to form a logical address, and providing a physical address corresponding to the logical address. When the effective address has a first effective address value, the address space identifier has a first address space identifier value, and the mapping modifier has a first mapping value, the physical address has a first physical address value. When the effective address has the first effective address value, the address space identifier has the first address space identifier value, and the mapping modifier has a second mapping value, the physical address has a second physical address value.
摘要翻译：一种方法包括提供有效地址，提供标识当前执行过程的地址空间标识符，提供映射修饰符以形成修改的地址空间标识符，其中映射修饰符基于在处理器外部生成的至少一个外部信号，使用有效地址和修改的地址空间标识符以形成逻辑地址，并提供对应于逻辑地址的物理地址。当有效地址具有第一有效地址值时，地址空间标识符具有第一地址空间标识符值，并且映射修饰符具有第一映射值，物理地址具有第一物理地址值。当有效地址具有第一有效地址值时，地址空间标识符具有第一地址空间标识符值，并且映射修饰符具有第二映射值，物理地址具有第二物理地址值。

8. 发明申请

US20070255924A1 Processor and method for altering address translation 有权
标题翻译：用于改变地址转换的处理器和方法
公开(公告)号：US20070255924A1
公开(公告)日：2007-11-01
申请号：US11413422
申请日：2006-04-28
申请人： William Moyer , Ray Marshall , Richard Soja
发明人： William Moyer , Ray Marshall , Richard Soja
IPC分类号： G06F12/00
CPC分类号： G06F12/1027
摘要： In a processor having an address translation table, a method includes providing a logical address and control signal. When the control signal has a first value, a first physical address is provided corresponding to the logical address, and when the control signal has a second value, a second physical address is provided. The first physical address and the second physical address are stored in at least one valid entry of the address translation table. In one case, the first physical address is stored in a first valid entry having a tag field which matches the logical address and the second physical address is stored in a second valid entry having a tag field which matches the logical address. Alternatively, the first physical address is stored in a first field of a first valid entry and the second physical address is stored in a second field of the first valid entry.
摘要翻译：在具有地址转换表的处理器中，一种方法包括提供逻辑地址和控制信号。当控制信号具有第一值时，对应于逻辑地址提供第一物理地址，并且当控制信号具有第二值时，提供第二物理地址。第一物理地址和第二物理地址存储在地址转换表的至少一个有效条目中。在一种情况下，第一物理地址存储在具有与逻辑地址匹配的标签字段的第一有效条目中，并且第二物理地址被存储在具有与逻辑地址匹配的标签字段的第二有效条目中。或者，第一物理地址存储在第一有效条目的第一字段中，并且第二物理地址存储在第一有效条目的第二字段中。

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