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1. 发明授权

US5072365A Direct memory access controller using prioritized interrupts for varying bus mastership 失效
标题翻译：直接存储器访问控制器使用优化中断来改变总线主控
公开(公告)号：US5072365A
公开(公告)日：1991-12-10
申请号：US457647
申请日：1989-12-27
申请人： Bradley G. Burgess , James B. Eifert , John P. Dunn
发明人： Bradley G. Burgess , James B. Eifert , John P. Dunn
IPC分类号： G06F13/28 , G06F13/34
CPC分类号： G06F13/34
摘要： A data processing system having a direct memory access controller (DMAC) which can be interrupted with a prioritized signal to vary bus mastership of a communication bus in the system. A prioritized interrupt signal is sent to a CPU when the DMAC has bus mastership. The CPU only informs the DMAC of the highest priority cumulative interrupt priority. With the use of a mask value, the interrupt may be selectively screened by the DMAC so that selective interrupts may remove bus mastership from the DMAC.

2. 发明授权

US5448744A Integrated circuit microprocessor with programmable chip select logic 失效
标题翻译：具有可编程芯片选择逻辑的集成电路微处理器
公开(公告)号：US5448744A
公开(公告)日：1995-09-05
申请号：US432423
申请日：1989-11-06
申请人： James B. Eifert , John J. Vaglica , James C. Smallwood , Mark W. McDermott , Hiroyuki Sugiyama , William P. LaViolette , Bradley G. Burgess
发明人： James B. Eifert , John J. Vaglica , James C. Smallwood , Mark W. McDermott , Hiroyuki Sugiyama , William P. LaViolette , Bradley G. Burgess
IPC分类号： G06F9/38 , G06F9/22 , G06F13/10
CPC分类号： G06F9/3877
摘要： An integrated circuit microprocessor has on-board programmable chip select logic. Each of several chip select outputs is individually programmable by means of one or more control register bit fields. For instance, each chip select is asserted for bus cycles within an address range whose starting address and block size are both programmable. In addition, each chip select can be programmed to be active on read cycles only, on write cycles only, or on both read and write cycles. Each chip select can be programmed to be active during interrupt acknowledge cycles only if the interrupt being acknowledged has the same priority level as has been programmed for that chip select. In addition, the timing of the assertion of each chip select is programmable to coincide with either the address strobe or data strobe of the bus cycle. The chip select logic is designed so that it is configured to come out of reset by producing an active chip select signal during the first bus cycle run by the processor following the reset. This chip select is appropriate for selecting a boot ROM, and may later be re-programmed for other use. The chip select logic is capable of supporting cycle-by-cycle dynamic bus sizing by asserting appropriate cycle termination signals. The chip select logic can also insert a programmable number of wait states into a bus cycle to accommodate slow peripherals or can cause a fast termination of a bus cycle to improve the utilization of fast peripherals.
摘要翻译：集成电路微处理器具有板载可编程芯片选择逻辑。几个芯片选择输出中的每一个可以通过一个或多个控制寄存器位字段单独编程。例如，每个芯片选择在起始地址和块大小均可编程的地址范围内被断言用于总线周期。此外，每个芯片选择都可以被编程为仅在读周期有效，仅在写周期或读周期和写周期。只有在确认中断与该芯片选择相同的优先级时，每个芯片选择才能在中断确认周期内被编程为有效。此外，每个芯片选择的断言的定时可编程为与总线周期的地址选通或数据选通一致。芯片选择逻辑被设计为使得其被配置为在复位之后由处理器运行的第一总线周期期间产生有效芯片选择信号而退出复位。该芯片选择适用于选择引导ROM，然后可以重新编程以供其他使用。芯片选择逻辑能够通过断言适当的周期终止信号来支持逐周期动态总线大小调整。芯片选择逻辑还可以将可编程的等待状态数插入总线周期以适应慢速外设，或者可能导致总线周期的快速终止，从而提高快速外设的利用率。

3. 发明授权

US5329621A Microprocessor which optimizes bus utilization based upon bus speed 失效
标题翻译：基于总线速度优化总线利用率的微处理器
公开(公告)号：US5329621A
公开(公告)日：1994-07-12
申请号：US425082
申请日：1989-10-23
申请人： Bradley G. Burgess , James B. Eifert , Michael S. Taborn
发明人： Bradley G. Burgess , James B. Eifert , Michael S. Taborn
IPC分类号： G06F9/38 , G06F9/28
CPC分类号： G06F9/3804
摘要： A data processing apparatus having a bus speed counter for determining the bus speed of a previous bus cycle. This previous bus speed information is then used to optimize bus utilization. This bus speed information is particularly useful for determining whether to run prefetch bus cycles during the execution of a conditional branch instruction. If previous bus cycles have been slow, prefetch procrastination can occurs until the branch condition resolves.
摘要翻译：一种具有用于确定先前总线周期的总线速度的总线速度计数器的数据处理装置。然后使用以前的总线速度信息来优化总线利用率。该总线速度信息对于在执行条件转移指令期间确定是否运行预取总线周期特别有用。如果以前的总线周期一直很慢，则可能会发生预取拖延，直到分支条件解决。

4. 发明授权

US5361392A Digital computing system with low power mode and special bus cycle therefor 失效
标题翻译：具有低功耗模式和特殊总线周期的数字计算系统
公开(公告)号：US5361392A
公开(公告)日：1994-11-01
申请号：US033992
申请日：1993-03-19
申请人： Antone L. Fourcroy , Mark W. McDermott , John P. Dunn , Bradley G. Burgess
发明人： Antone L. Fourcroy , Mark W. McDermott , John P. Dunn , Bradley G. Burgess
IPC分类号： G06F1/04 , G06F1/32 , G06F15/78 , G06F9/30 , G06F9/46 , G06F11/20 , G06F13/24
CPC分类号： G06F9/30083 , G06F1/3203 , G06F9/30167
摘要： A digital computing system having a low power mode of operation includes a mechanism for communicating, prior to entering the low power mode, information determinative of which events shall be capable of causing the termination of the low power mode. An integrated circuit microcomputer enters a low power mode in response to executing an LPSTOP instruction. Only reset events and those interrupt events having a priority level sufficiently high to pass an interrupt mask are capable of causing the termination of the low power mode. The LPSTOP instruction causes immediate data to be loaded into a status register, resetting the interrupt mask bits. The interrupt mask is then written, by means of a special bus cycle, into an interrupt mask register in a sub-system within the microcomputer. This subsystem then shuts down the clock signals to the remainder of the microcomputer, leaving only this sub-system active. The active sub-system performs a comparison of the priority levels of received interrupt requests to the interrupt mask during the low power mode. Only if the priority level of an interrupt is sufficiently high are the clock signals resumed, thus terminating the low power mode.
摘要翻译：具有低功率操作模式的数字计算系统包括用于在进入低功率模式之前通信的信息，该信息确定哪些事件将能够导致低功率模式的终止。响应于执行LPSTOP指令，集成电路微计算机进入低功率模式。只有重置事件和具有足够高的优先级才能通过中断掩码的中断事件才能导致低功率模式的终止。 LPSTOP指令将立即数据加载到状态寄存器中，复位中断屏蔽位。然后通过专用总线周期将中断屏蔽写入微机内的子系统中的中断屏蔽寄存器。该子系统然后将时钟信号关闭到微计算机的其余部分，只剩下这个子系统。在低功耗模式下，有源子系统对接收到的中断请求的优先级进行中断屏蔽的比较。只有当中断的优先级足够高时，恢复时钟信号，从而终止低功耗模式。

5. 发明授权

US06202130B1 Data processing system for processing vector data and method therefor 失效
标题翻译：用于处理矢量数据的数据处理系统及其方法
公开(公告)号：US06202130B1
公开(公告)日：2001-03-13
申请号：US09061975
申请日：1998-04-17
申请人： Hunter Ledbetter Scales, III , Keith Everett Diefendorff , Brett Olsson , Pradeep Kumar Dubey , Ronald Ray Hochsprung , Bradford Byron Beavers , Bradley G. Burgess , Michael Dean Snyder , Cathy May , Edward John Silha
发明人： Hunter Ledbetter Scales, III , Keith Everett Diefendorff , Brett Olsson , Pradeep Kumar Dubey , Ronald Ray Hochsprung , Bradford Byron Beavers , Bradley G. Burgess , Michael Dean Snyder , Cathy May , Edward John Silha
IPC分类号： G06F1200
CPC分类号： G06F9/30047 , G06F9/30101 , G06F12/0862 , G06F2212/6028
摘要： A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (10) prefetches data elements of a vector into the first memory prior to processing such data elements. If a requested data element is not present in the first memory, a load request is issued to the second memory and to lower levels of the memory hierarchy until the requested data element is finally retrieved and stored in the first memory. The data processor (10) continues to prefetch subsequent data elements of the vector by considering the length of the data element and the stride of the vector. In one embodiment, the data processor (10) prefetches the vector into the first memory in response to a single data stream touch load (DST) instruction (100).
摘要翻译：数据处理系统包括耦合到具有诸如L1数据高速缓存（16）的第一存储器的存储器系统的数据处理器（10），其布置在较低分层级的第二存储器（例如L2高速缓存）。在处理这些数据元素之前，数据处理器（10）将向量的数据元素预取到第一存储器中。如果请求的数据元素不存在于第一存储器中，则向第二存储器发出加载请求，并将存储器层级降低到最低限度，直到所请求的数据元素被最终检索并存储在第一存储器中。数据处理器（10）通过考虑数据元素的长度和向量的步幅继续预取向量的后续数据元素。在一个实施例中，数据处理器（10）响应于单个数据流接触负载（DST）指令（100）将矢量预取到第一存储器中。

6. 发明授权

US6157999A Data processing system having a synchronizing link stack and method thereof 失效
标题翻译：具有同步链路栈的数据处理系统及其方法
公开(公告)号：US6157999A
公开(公告)日：2000-12-05
申请号：US868467
申请日：1997-06-03
申请人： Paul C. Rossbach , Albert R. Kennedy , Jeffrey P. Rupley, II , Bradley G. Burgess
发明人： Paul C. Rossbach , Albert R. Kennedy , Jeffrey P. Rupley, II , Bradley G. Burgess
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3844 , G06F9/4426
摘要： When a request to branch to an address stored in a return memory location (440) occurs, a busy bit is used to determine whether the return memory location (440) contains updated information. When the information is not updated, a predicted address is provided to the prediction verifier (460) by the link stack (410). Once the busy bit is valid, the prediction verifier (460) determines if a proper prediction was made. When an improper prediction was made, the update portion (415) of the link stack (410) based on information from the comparator (425) determines if a value stored in the link stack (410) matches the value stored in the return memory location (440). The link stack (410) is synchronized based upon a favorable comparison indicating the return memory location value matches a value in the link stack. If a match is not found, the predicted address is placed back on the link stack or alternatively the link stack is cleared.
摘要翻译：当发生分支到存储在返回存储器位置（440）中的地址的请求时，使用忙位来确定返回存储器位置（440）是否包含更新的信息。当不更新信息时，通过链路栈（410）将预测地址提供给预测验证器（460）。一旦忙位有效，预测验证器（460）确定是否进行了适当的预测。当进行不正确的预测时，基于来自比较器（425）的信息，链接堆栈（410）的更新部分（415）确定存储在链接堆栈（410）中的值是否与存储在返回存储器位置中的值相匹配（440）。基于指示返回存储器位置值与链路栈中的值匹配的有利比较，链路栈（410）被同步。如果没有找到匹配项，则将预测的地址放回到链路栈，或者链路栈被清除。

7. 发明授权

US07921293B2 Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment 有权
标题翻译：在多处理器环境中单方面加载安全操作系统的装置和方法
公开(公告)号：US07921293B2
公开(公告)日：2011-04-05
申请号：US11340181
申请日：2006-01-24
申请人： Michael A. Kozuch , James A. Sutton, II , David Grawrock , Gilbert Neiger , Richard A. Uhlig , Bradley G. Burgess , David I. Poisner , Clifford D. Hall , Andy Glew , Lawrence O. Smith, III , Robert George
发明人： Michael A. Kozuch , James A. Sutton, II , David Grawrock , Gilbert Neiger , Richard A. Uhlig , Bradley G. Burgess , David I. Poisner , Clifford D. Hall , Andy Glew , Lawrence O. Smith, III , Robert George
IPC分类号： H04L9/00 , G06F21/00
CPC分类号： G06F21/57
摘要： An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value to establish security verification of secure software within the secure memory environment.
摘要翻译：描述了在多处理器环境内单方面加载安全操作系统的装置和方法。该方法包括当检测到当前活动的负载安全区域操作时忽略接收的负载安全区域指令。否则，响应于接收到的负载安全区域指令，引导存储器保护元件以形成安全存储器环境。一旦定向，就禁止对一个或多个受保护的存储器区域进行未经授权的读/写访问。最后，一个或多个受保护的存储器区域的加密散列值作为安全的软件识别值存储在摘要信息库中。一旦存储，外部代理可以请求访问数字签名的软件标识值以建立安全存储器环境内的安全软件的安全验证。

8. 发明授权

US5392228A Result normalizer and method of operation 失效
标题翻译：结果规范和操作方法
公开(公告)号：US5392228A
公开(公告)日：1995-02-21
申请号：US161361
申请日：1993-12-06
申请人： Bradley G. Burgess , Timothy A. Elliott , Christopher H. Olson , Terence M. Potter
发明人： Bradley G. Burgess , Timothy A. Elliott , Christopher H. Olson , Terence M. Potter
IPC分类号： G06F7/485 , G06F5/01 , G06F7/00 , G06F7/50 , G06F7/76
CPC分类号： G06F7/485 , G06F5/012
摘要： A result normalizer (58) for use with an adder (56) generates a mask in two stages that indicates the location of the leading one in the adder result. In the first stage, a leading zero anticipator (68) determines the position to within two digits. In the second stage, a count leading zero indicator (70) determines the position to a single digit. The mask is used to control the number of digits that each stage of a multiplexer array (66) shifts the adder result. The output of the multiplexer array thereby contains a leading one. The result normalizer may be advantageously used in high performance applications such as in a floating point execution unit in a data processor or in digital signal processing systems.
摘要翻译：与加法器（56）一起使用的结果归一化器（58）在两个阶段中生成指示加法器结果中前导序列的位置的掩码。在第一阶段，领先的零预测者（68）将位置确定在两位数之内。在第二阶段中，计数前导零指示符（70）确定位置到单个数字。该掩码用于控制多路复用器阵列（66）的每个级移位加法器结果的位数。因此，多路复用器阵列的输出包含一个前导的。结果归一化器可以有利地用于高性能应用中，例如在数据处理器或数字信号处理系统中的浮点执行单元中。

9. 发明申请

US20130009697A1 PIPELINE POWER GATING 有权
标题翻译：管道功率补偿
公开(公告)号：US20130009697A1
公开(公告)日：2013-01-10
申请号：US13176842
申请日：2011-07-06
申请人： Daniel W. Bailey , Aaron S. Rogers , James J. Montanaro , Bradley G. Burgess , Peter J. Hannan
发明人： Daniel W. Bailey , Aaron S. Rogers , James J. Montanaro , Bradley G. Burgess , Peter J. Hannan
IPC分类号： G05F3/02
CPC分类号： H03K19/0013 , H03K19/0016
摘要： Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.
摘要翻译：通过唤醒多个门以允许电流流动响应于使得能够对源存储元件进行时钟的任何源时钟使能信号的断言，耦合在源存储元件和目的地存储元件之间的多个栅极中的泄漏电流减小。响应于确定目的地时钟使能信号并且所有一个或多个源时钟使能信号被断言，门被睡眠以减少多个门中的泄漏电流，目的地时钟使能信号使得能够对目的地存储元件进行时钟。

10. 发明授权

US06477640B1 Apparatus and method for predicting multiple branches and performing out-of-order branch resolution 失效
标题翻译：用于预测多个分支并执行无序分支分辨率的装置和方法
公开(公告)号：US06477640B1
公开(公告)日：2002-11-05
申请号：US09659401
申请日：2000-09-11
申请人： Jeffrey Pidge Rupley, II , Marvin A. Denman , Bradley G. Burgess , David C. Holloway
发明人： Jeffrey Pidge Rupley, II , Marvin A. Denman , Bradley G. Burgess , David C. Holloway
IPC分类号： G06F1560
CPC分类号： G06F9/3851 , G06F9/3844 , G06F9/3861
摘要： A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.
摘要翻译：分支预测单元装置和方法使用指令缓冲器（20），完成单元（24）和分支预测单元（BPU）（28）。指令缓冲器（20）和/或完成单元（24）包含包含有效位和流标识符（SID）位的多个指令条目。分支预测单元包含多个分支预测缓冲器（28a-28c）。 SID位用于将单元（20和24）中的待执行和执行的指令与位于缓冲器（28a-28c）中的预测分支相关的指令流相关联。 SID位以及与缓冲器（28a-28c）相关联的老化位用于执行有效的分支预测，分支解决/退出和分支错误预测恢复。

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