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1. 发明授权

US07024555B2 Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment 失效
公开(公告)号：US07024555B2
公开(公告)日：2006-04-04
申请号：US10043843
申请日：2001-11-01
申请人： Michael A. Kozuch , James A. Sutton, II , David Grawrock , Gilbert Neiger , Richard A. Uhlig , Bradley G. Burgess , David I. Poisner , Clifford D. Hall , Andy Glew , Lawrence O. Smith, III , Robert George
发明人： Michael A. Kozuch , James A. Sutton, II , David Grawrock , Gilbert Neiger , Richard A. Uhlig , Bradley G. Burgess , David I. Poisner , Clifford D. Hall , Andy Glew , Lawrence O. Smith, III , Robert George
IPC分类号： G06F1/26
CPC分类号： G06F21/57
摘要： An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value in order to establish security verification of secure software within the secure memory environment.

2. 发明授权

US07921293B2 Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment 有权
标题翻译：在多处理器环境中单方面加载安全操作系统的装置和方法
公开(公告)号：US07921293B2
公开(公告)日：2011-04-05
申请号：US11340181
申请日：2006-01-24
申请人： Michael A. Kozuch , James A. Sutton, II , David Grawrock , Gilbert Neiger , Richard A. Uhlig , Bradley G. Burgess , David I. Poisner , Clifford D. Hall , Andy Glew , Lawrence O. Smith, III , Robert George
发明人： Michael A. Kozuch , James A. Sutton, II , David Grawrock , Gilbert Neiger , Richard A. Uhlig , Bradley G. Burgess , David I. Poisner , Clifford D. Hall , Andy Glew , Lawrence O. Smith, III , Robert George
IPC分类号： H04L9/00 , G06F21/00
CPC分类号： G06F21/57
摘要： An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value to establish security verification of secure software within the secure memory environment.
摘要翻译：描述了在多处理器环境内单方面加载安全操作系统的装置和方法。该方法包括当检测到当前活动的负载安全区域操作时忽略接收的负载安全区域指令。否则，响应于接收到的负载安全区域指令，引导存储器保护元件以形成安全存储器环境。一旦定向，就禁止对一个或多个受保护的存储器区域进行未经授权的读/写访问。最后，一个或多个受保护的存储器区域的加密散列值作为安全的软件识别值存储在摘要信息库中。一旦存储，外部代理可以请求访问数字签名的软件标识值以建立安全存储器环境内的安全软件的安全验证。

3. 发明授权

US06202130B1 Data processing system for processing vector data and method therefor 失效
标题翻译：用于处理矢量数据的数据处理系统及其方法
公开(公告)号：US06202130B1
公开(公告)日：2001-03-13
申请号：US09061975
申请日：1998-04-17
申请人： Hunter Ledbetter Scales, III , Keith Everett Diefendorff , Brett Olsson , Pradeep Kumar Dubey , Ronald Ray Hochsprung , Bradford Byron Beavers , Bradley G. Burgess , Michael Dean Snyder , Cathy May , Edward John Silha
发明人： Hunter Ledbetter Scales, III , Keith Everett Diefendorff , Brett Olsson , Pradeep Kumar Dubey , Ronald Ray Hochsprung , Bradford Byron Beavers , Bradley G. Burgess , Michael Dean Snyder , Cathy May , Edward John Silha
IPC分类号： G06F1200
CPC分类号： G06F9/30047 , G06F9/30101 , G06F12/0862 , G06F2212/6028
摘要： A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (10) prefetches data elements of a vector into the first memory prior to processing such data elements. If a requested data element is not present in the first memory, a load request is issued to the second memory and to lower levels of the memory hierarchy until the requested data element is finally retrieved and stored in the first memory. The data processor (10) continues to prefetch subsequent data elements of the vector by considering the length of the data element and the stride of the vector. In one embodiment, the data processor (10) prefetches the vector into the first memory in response to a single data stream touch load (DST) instruction (100).
摘要翻译：数据处理系统包括耦合到具有诸如L1数据高速缓存（16）的第一存储器的存储器系统的数据处理器（10），其布置在较低分层级的第二存储器（例如L2高速缓存）。在处理这些数据元素之前，数据处理器（10）将向量的数据元素预取到第一存储器中。如果请求的数据元素不存在于第一存储器中，则向第二存储器发出加载请求，并将存储器层级降低到最低限度，直到所请求的数据元素被最终检索并存储在第一存储器中。数据处理器（10）通过考虑数据元素的长度和向量的步幅继续预取向量的后续数据元素。在一个实施例中，数据处理器（10）响应于单个数据流接触负载（DST）指令（100）将矢量预取到第一存储器中。

4. 发明授权

US6157999A Data processing system having a synchronizing link stack and method thereof 失效
标题翻译：具有同步链路栈的数据处理系统及其方法
公开(公告)号：US6157999A
公开(公告)日：2000-12-05
申请号：US868467
申请日：1997-06-03
申请人： Paul C. Rossbach , Albert R. Kennedy , Jeffrey P. Rupley, II , Bradley G. Burgess
发明人： Paul C. Rossbach , Albert R. Kennedy , Jeffrey P. Rupley, II , Bradley G. Burgess
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3844 , G06F9/4426
摘要： When a request to branch to an address stored in a return memory location (440) occurs, a busy bit is used to determine whether the return memory location (440) contains updated information. When the information is not updated, a predicted address is provided to the prediction verifier (460) by the link stack (410). Once the busy bit is valid, the prediction verifier (460) determines if a proper prediction was made. When an improper prediction was made, the update portion (415) of the link stack (410) based on information from the comparator (425) determines if a value stored in the link stack (410) matches the value stored in the return memory location (440). The link stack (410) is synchronized based upon a favorable comparison indicating the return memory location value matches a value in the link stack. If a match is not found, the predicted address is placed back on the link stack or alternatively the link stack is cleared.
摘要翻译：当发生分支到存储在返回存储器位置（440）中的地址的请求时，使用忙位来确定返回存储器位置（440）是否包含更新的信息。当不更新信息时，通过链路栈（410）将预测地址提供给预测验证器（460）。一旦忙位有效，预测验证器（460）确定是否进行了适当的预测。当进行不正确的预测时，基于来自比较器（425）的信息，链接堆栈（410）的更新部分（415）确定存储在链接堆栈（410）中的值是否与存储在返回存储器位置中的值相匹配（440）。基于指示返回存储器位置值与链路栈中的值匹配的有利比较，链路栈（410）被同步。如果没有找到匹配项，则将预测的地址放回到链路栈，或者链路栈被清除。

5. 发明授权

US5392228A Result normalizer and method of operation 失效
标题翻译：结果规范和操作方法
公开(公告)号：US5392228A
公开(公告)日：1995-02-21
申请号：US161361
申请日：1993-12-06
申请人： Bradley G. Burgess , Timothy A. Elliott , Christopher H. Olson , Terence M. Potter
发明人： Bradley G. Burgess , Timothy A. Elliott , Christopher H. Olson , Terence M. Potter
IPC分类号： G06F7/485 , G06F5/01 , G06F7/00 , G06F7/50 , G06F7/76
CPC分类号： G06F7/485 , G06F5/012
摘要： A result normalizer (58) for use with an adder (56) generates a mask in two stages that indicates the location of the leading one in the adder result. In the first stage, a leading zero anticipator (68) determines the position to within two digits. In the second stage, a count leading zero indicator (70) determines the position to a single digit. The mask is used to control the number of digits that each stage of a multiplexer array (66) shifts the adder result. The output of the multiplexer array thereby contains a leading one. The result normalizer may be advantageously used in high performance applications such as in a floating point execution unit in a data processor or in digital signal processing systems.
摘要翻译：与加法器（56）一起使用的结果归一化器（58）在两个阶段中生成指示加法器结果中前导序列的位置的掩码。在第一阶段，领先的零预测者（68）将位置确定在两位数之内。在第二阶段中，计数前导零指示符（70）确定位置到单个数字。该掩码用于控制多路复用器阵列（66）的每个级移位加法器结果的位数。因此，多路复用器阵列的输出包含一个前导的。结果归一化器可以有利地用于高性能应用中，例如在数据处理器或数字信号处理系统中的浮点执行单元中。

6. 发明授权

US5072365A Direct memory access controller using prioritized interrupts for varying bus mastership 失效
标题翻译：直接存储器访问控制器使用优化中断来改变总线主控
公开(公告)号：US5072365A
公开(公告)日：1991-12-10
申请号：US457647
申请日：1989-12-27
申请人： Bradley G. Burgess , James B. Eifert , John P. Dunn
发明人： Bradley G. Burgess , James B. Eifert , John P. Dunn
IPC分类号： G06F13/28 , G06F13/34
CPC分类号： G06F13/34
摘要： A data processing system having a direct memory access controller (DMAC) which can be interrupted with a prioritized signal to vary bus mastership of a communication bus in the system. A prioritized interrupt signal is sent to a CPU when the DMAC has bus mastership. The CPU only informs the DMAC of the highest priority cumulative interrupt priority. With the use of a mask value, the interrupt may be selectively screened by the DMAC so that selective interrupts may remove bus mastership from the DMAC.

7. 发明申请

US20130009697A1 PIPELINE POWER GATING 有权
标题翻译：管道功率补偿
公开(公告)号：US20130009697A1
公开(公告)日：2013-01-10
申请号：US13176842
申请日：2011-07-06
申请人： Daniel W. Bailey , Aaron S. Rogers , James J. Montanaro , Bradley G. Burgess , Peter J. Hannan
发明人： Daniel W. Bailey , Aaron S. Rogers , James J. Montanaro , Bradley G. Burgess , Peter J. Hannan
IPC分类号： G05F3/02
CPC分类号： H03K19/0013 , H03K19/0016
摘要： Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.
摘要翻译：通过唤醒多个门以允许电流流动响应于使得能够对源存储元件进行时钟的任何源时钟使能信号的断言，耦合在源存储元件和目的地存储元件之间的多个栅极中的泄漏电流减小。响应于确定目的地时钟使能信号并且所有一个或多个源时钟使能信号被断言，门被睡眠以减少多个门中的泄漏电流，目的地时钟使能信号使得能够对目的地存储元件进行时钟。

8. 发明授权

US06477640B1 Apparatus and method for predicting multiple branches and performing out-of-order branch resolution 失效
标题翻译：用于预测多个分支并执行无序分支分辨率的装置和方法
公开(公告)号：US06477640B1
公开(公告)日：2002-11-05
申请号：US09659401
申请日：2000-09-11
申请人： Jeffrey Pidge Rupley, II , Marvin A. Denman , Bradley G. Burgess , David C. Holloway
发明人： Jeffrey Pidge Rupley, II , Marvin A. Denman , Bradley G. Burgess , David C. Holloway
IPC分类号： G06F1560
CPC分类号： G06F9/3851 , G06F9/3844 , G06F9/3861
摘要： A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.
摘要翻译：分支预测单元装置和方法使用指令缓冲器（20），完成单元（24）和分支预测单元（BPU）（28）。指令缓冲器（20）和/或完成单元（24）包含包含有效位和流标识符（SID）位的多个指令条目。分支预测单元包含多个分支预测缓冲器（28a-28c）。 SID位用于将单元（20和24）中的待执行和执行的指令与位于缓冲器（28a-28c）中的预测分支相关的指令流相关联。 SID位以及与缓冲器（28a-28c）相关联的老化位用于执行有效的分支预测，分支解决/退出和分支错误预测恢复。

9. 发明授权

US5034922A Intelligent electrically erasable, programmable read-only memory with improved read latency 失效
标题翻译：智能电可擦除可编程只读存储器，具有改进的读延迟
公开(公告)号：US5034922A
公开(公告)日：1991-07-23
申请号：US135945
申请日：1987-12-21
申请人： Bradley G. Burgess
发明人： Bradley G. Burgess
IPC分类号： G11C16/26 , G11C16/32
CPC分类号： G11C16/26 , G11C16/32
摘要： An intelligent electrically erasable, programmable read-only memory achieves improved worst-case read operation latency by allowing for the interruption of write operations by subsequently received read requests. In the preferred embodiment, a state machine controller executes write operations by an iterative process of write pulses and write verify cycles. In addition, cells are erased prior to being written to by a similar iterative process. Both the write operations and the erase operations may be interrupted by read requests received after the write operation has begun execution. To avoid reading incorrect data in the case of a read operation at the same address as an interrupted write operation, a comparator matches read operation addresses with latched write operation addresses and provides the read operation data from a write data latch in the case of a match.
摘要翻译：智能电可擦除可编程只读存储器通过允许随后接收到的读请求中断写操作来实现改进的最坏情况读操作等待时间。在优选实施例中，状态机控制器通过写入脉冲和写入验证周期的迭代处理执行写入操作。此外，在通过类似的迭代过程被写入之前，单元被擦除。写入操作和擦除操作都可能在写操作开始执行之后被读取请求中断。为了避免在与中断的写入操作相同的地址处读取操作的情况下读取不正确的数据，比较器将读操作地址与锁存的写操作地址相匹配，并且在匹配的情况下从写数据锁存器提供读操作数据。

10. 发明授权

US5500943A Data processor with rename buffer and FIFO buffer for in-order instruction completion 失效
标题翻译：具有重命名缓冲器和FIFO缓冲器的数据处理器，用于按顺序指令完成
公开(公告)号：US5500943A
公开(公告)日：1996-03-19
申请号：US442913
申请日：1995-05-17
申请人： Ying-wai Ho , Bradley G. Burgess
发明人： Ying-wai Ho , Bradley G. Burgess
IPC分类号： G06F9/32 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30094 , G06F9/3863
摘要： A data processor has first calculation circuitry (26), a rename buffer (34), and a queue (36). The first calculation circuitry generates a first and a second result from supplied operands and received programmed instructions. The rename buffer is coupled to the first calculation circuitry and stores a series of first results received from the first calculation circuitry. The rename buffer outputs the series of first results to a first predetermined register. The queue is also coupled to the first calculation circuitry and stores a series of second results. The queue outputs the sequence of second results to a second predetermined register in the same the sequence as it received the second results from the first calculation circuitry.
摘要翻译：数据处理器具有第一计算电路（26），重命名缓冲器（34）和队列（36）。第一计算电路从提供的操作数和接收的编程指令产生第一和第二结果。重命名缓冲器耦合到第一计算电路并存储从第一计算电路接收的一系列第一结果。重命名缓冲器将一系列第一结果输出到第一预定寄存器。队列还耦合到第一计算电路并存储一系列第二结果。队列以与从第一计算电路接收到第二结果的顺序相同的顺序将第二结果的序列输出到第二预定寄存器。

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