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1. 发明授权

US06378018B1 Memory device and system including a low power interface 有权
标题翻译：存储器件和系统包括低功率接口
公开(公告)号：US06378018B1
公开(公告)日：2002-04-23
申请号：US09169506
申请日：1998-10-09
申请人： Ely K. Tsern , Thomas J. Holman , Richard M. Barth , Andrew V. Anderson , Paul G. Davis , Craig E. Hampel , Donald C. Stark , Abhijit M. Abhyankar
发明人： Ely K. Tsern , Thomas J. Holman , Richard M. Barth , Andrew V. Anderson , Paul G. Davis , Craig E. Hampel , Donald C. Stark , Abhijit M. Abhyankar
IPC分类号： G06F1300
CPC分类号： G06F13/4243 , G06F13/1694 , Y02D10/14 , Y02D10/151
摘要： A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure. The memory controller may be configured to apply control information to the interconnect structure as an encoded device identification word. The memory devices may each include a decoder for interpreting the encoded device identification word. The memory controller may be configured to apply a memory device selection signal to the interconnect structure to selectively enable the memory devices.
摘要翻译：存储器系统包括具有高速通道和低速通道的互连结构。具有接口电路的存储器件耦合到互连结构。接口电路包括用于耦合到高速通道的高功率接口和用于耦合到低速通道的低功率接口。存储器件在低功率模式和高功率模式下工作。存储器控制器耦合到互连结构的高速通道和低速通道。存储器控制器被配置为通过低速信道发送控制信息以设置存储器件的功率模式。存储器件在低功率模式下工作，在此期间高功率接收器电路被关闭。存储器装置还可以在休眠模式下工作，在此模式期间内部时钟补偿电路被保留以保持相位信息。存储器系统可以包括耦合到互连结构的菊花链引导件的多个存储器件。存储器控制器可以被配置为将控制信息作为编码设备标识字应用于互连结构。存储器件可以各自包括用于解释编码器件识别字的解码器。存储器控制器可以被配置为将存储器件选择信号施加到互连结构以选择性地启用存储器件。

2. 发明授权

US06226757B1 Apparatus and method for bus timing compensation 有权
标题翻译：总线定时补偿的装置和方法
公开(公告)号：US06226757B1
公开(公告)日：2001-05-01
申请号：US09169245
申请日：1998-10-09
申请人： Frederick A. Ware , Richard M. Barth , Donald C. Stark , Craig E. Hampel , Ely K. Tsern , Abhijit M. Abhyankar , Thomas J. Holman , Andrew V. Anderson , Peter D. MacWilliams
发明人： Frederick A. Ware , Richard M. Barth , Donald C. Stark , Craig E. Hampel , Ely K. Tsern , Abhijit M. Abhyankar , Thomas J. Holman , Andrew V. Anderson , Peter D. MacWilliams
IPC分类号： G06F104
CPC分类号： G06F13/4226
摘要： A digital system includes a clock line carrying a clock signal and a communication bus with a signal time of flight longer than a cycle of the clock signal. A master device is connected to the communication bus and the clock line. The master device selectively applies signals to the communication bus. A set of slave devices are connected to the communication bus and the clock line. Each slave device of the set of slave devices has an associated latency delay arising from its position on the communication bus. Each slave device includes delay circuitry to compensate for the associated latency delay such that the master device observes a uniform minimum latency for each slave device in response to applying signals to the communication bus.
摘要翻译：一个数字系统包括一个带有时钟信号的时钟线和一个具有比时钟信号周期长的信号时间的通信总线。主设备连接到通信总线和时钟线。主设备选择性地向通信总线施加信号。一组从设备连接到通信总线和时钟线。一组从设备的每个从设备具有由其在通信总线上的位置产生的相关联的延迟延迟。每个从设备包括延迟电路以补偿相关联的延迟延迟，使得主设备响应于向通信总线应用信号而观察到每个从设备的均匀最小等待时间。

3. 发明授权

US6075730A High performance cost optimized memory with delayed memory writes 有权
标题翻译：高性能的成本优化了内存延迟记忆
公开(公告)号：US6075730A
公开(公告)日：2000-06-13
申请号：US169729
申请日：1998-10-09
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen , Thomas J. Holman , Andrew V. Anderson , Peter D. MacWilliams
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen , Thomas J. Holman , Andrew V. Anderson , Peter D. MacWilliams
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1072 , G11C2207/229
摘要： A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.
摘要翻译：存储器件包括具有控制引脚和双向数据引脚的互连。内存核心存储数据。存储器接口电路连接到互连和存储器核。存储器接口电路包括延迟电路，以在存储器核心写入事务期间建立写入延迟，使得存储器核心写入事务具有基本上等同于存储器核心读取事务的处理时间。延迟电路将存储器核心写入事务延迟一段时间，该时间对应于信号在互连上行进所需的时间。

4. 发明授权

US06345009B1 Apparatus and method for refreshing subsets of memory devices in a memory system 有权
标题翻译：用于刷新存储器系统中存储器件子集的装置和方法
公开(公告)号：US06345009B1
公开(公告)日：2002-02-05
申请号：US09658465
申请日：2000-09-08
申请人： Ely K. Tsern , Richard M. Barth , Paul G. Davis , Craig E. Hampel , Thomas J. Holman , Andrew V. Anderson
发明人： Ely K. Tsern , Richard M. Barth , Paul G. Davis , Craig E. Hampel , Thomas J. Holman , Andrew V. Anderson
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A memory system includes a set of memory devices. An interconnect structure links the set of memory devices to one another. A memory controller is connected to the interconnect structure. The memory controller is configured to apply a control signal to the interconnect structure such that a specified subset of the set of memory devices performs a refresh operation.
摘要翻译：存储器系统包括一组存储器件。互连结构将存储器件集合彼此连接。存储器控制器连接到互连结构。存储器控制器被配置为将控制信号施加到互连结构，使得该组存储器件的指定子集执行刷新操作。

5. 发明授权

US06178130B1 Apparatus and method for refreshing subsets of memory devices in a memory system 有权
标题翻译：用于刷新存储器系统中存储器件子集的装置和方法
公开(公告)号：US06178130B1
公开(公告)日：2001-01-23
申请号：US09169590
申请日：1998-10-09
申请人： Ely K. Tsern , Richard M. Barth , Paul G. Davis , Craig E. Hampel , Thomas J. Holman , Andrew V. Anderson
发明人： Ely K. Tsern , Richard M. Barth , Paul G. Davis , Craig E. Hampel , Thomas J. Holman , Andrew V. Anderson
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A memory system includes a set of memory devices. An interconnect structure links the set of memory devices to one another. A memory controller is connected to the interconnect structure. The memory controller is configured to apply a control signal to the interconnect structure such that a specified subset of the set of memory devices performs a refresh operation.
摘要翻译：存储器系统包括一组存储器件。互连结构将存储器件集合彼此连接。存储器控制器连接到互连结构。存储器控制器被配置为将控制信号施加到互连结构，使得该组存储器件的指定子集执行刷新操作。

6. 发明授权

US06226754B1 Apparatus and method for device timing compensation 有权
标题翻译：器件定时补偿的装置和方法
公开(公告)号：US06226754B1
公开(公告)日：2001-05-01
申请号：US09169687
申请日：1998-10-09
申请人： Frederick A. Ware , Richard M. Barth , Donald C. Stark , Craig E. Hampel , Ely K. Tsern , Abhijit M. Abhyankar
发明人： Frederick A. Ware , Richard M. Barth , Donald C. Stark , Craig E. Hampel , Ely K. Tsern , Abhijit M. Abhyankar
IPC分类号： G06F104
CPC分类号： G11C7/1072 , G11C7/22
摘要： An electronic device with device timing constraints includes a set of connections coupled to an interconnect structure that carries row and column commands. A memory core stores data. A memory interface is connect to the set of connections and the memory core. The memory interface includes circuitry for generating memory core timing signals in accordance with the row commands and the column commands. The memory core timing signals have timing constraints to insure correct memory core operation. The memory interface circuitry includes individual delay components for adjusting the timing of selected timing signals of the memory core timing signals.
摘要翻译：具有设备定时约束的电子设备包括耦合到承载行和列命令的互连结构的一组连接。内存核心存储数据。存储器接口连接到一组连接和存储器核心。存储器接口包括用于根据行命令和列命令产生存储器核心定时信号的电路。存储器核心定时信号具有时序约束，以确保正确的存储器核心操作。存储器接口电路包括用于调整存储器核心定时信号的选定定时信号的定时的各个延迟部件。

7. 发明授权

US08560797B2 Method and apparatus for indicating mask information 有权
标题翻译：用于指示掩模信息的方法和装置
公开(公告)号：US08560797B2
公开(公告)日：2013-10-15
申请号：US13421701
申请日：2012-03-15
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasborro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasborro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.
摘要翻译：一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括一个接口，用于在第一组多条引线上向DRAM发送一个第一代码，以指示第一个数据要写入DRAM，列地址以指示要写入第一数据的DRAM中的存储器核的列位置。该接口还用于发送第二代码以指示是否将第一数据的掩码信息发送到DRAM。如果第二代码指示将发送掩码信息，则在发送第二代码之后发送列地址的一部分和掩码信息的一部分。接口进一步通过与第一多个电线分开的第二多个电线将DRAM发送到第一数据。

8. 发明申请

US20120173811A1 Method and Apparatus for Delaying Write Operations 审中-公开
标题翻译：延迟写入操作的方法和装置
公开(公告)号：US20120173811A1
公开(公告)日：2012-07-05
申请号：US13421753
申请日：2012-03-15
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit to the DRAM a first code to indicate that first data is to be written to the DRAM. The first code is to be sampled by the DRAM and held by the DRAM for a first period of time before it is issued inside the DRAM. The interface is further to transmit the first data that is to be sampled by the DRAM after a second period of time has elapsed from when the first code is sampled by the DRAM. The interface is further to transmit a second code, different from the first code, to indicate that second data is to be read from the DRAM. The second code is to be sampled by the DRAM on one or more edges of the external clock signal.
摘要翻译：一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括用于向DRAM发送第一代码以指示要将第一数据写入DRAM的接口。第一代码将由DRAM采样并由DRAM在DRAM发出之前的第一时间段内保持。该接口在从DRAM的第一代码被采样起经过了第二时间段之后，进一步发送由DRAM采样的第一数据。该接口还用于发送与第一代码不同的第二代码，以指示要从DRAM读取第二数据。第二个代码由外部时钟信号的一个或多个边缘上的DRAM采样。

9. 发明授权

US08019958B2 Memory write signaling and methods thereof 有权
标题翻译：存储器写入信令及其方法
公开(公告)号：US08019958B2
公开(公告)日：2011-09-13
申请号：US12875483
申请日：2010-09-03
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarre , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarre , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.
摘要翻译：在控制存储器件的方法中，以下是通过第一组互连资源传送的：指定一行存储器单元的激活的第一命令; 指定写操作的第二命令，其中写数据被写入行; 指定在写入数据写入之后是否发生预充电的一点; 以及指定是否将为写入操作发布数据掩码信息的代码。如果代码指定信息将被发出，则在传送代码之后，通过第一组互连资源传送指定是否选择性地写入写入数据的部分的信息。要写入与写入操作相关的写入数据通过与第一组互连资源分开的第二组互连资源传送。

10. 发明授权

US07496709B2 Integrated circuit memory device having delayed write timing based on read response time 有权
标题翻译：具有基于读取响应时间的延迟写入定时的集成电路存储器件
公开(公告)号：US07496709B2
公开(公告)日：2009-02-24
申请号：US11953803
申请日：2007-12-10
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.
摘要翻译：集成电路存储器件包括用于存储写入数据的存储器核心，用于接收写入数据的第一组互连资源以及用于接收与写入数据相关联的写入命令的第二组互连资源。指示掩码信息是否包括在写入命令中的信息，其中当包括在写入命令中时，掩码信息指定是否选择性地将写入数据的部分写入存储器核心。

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