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1. 发明授权

US5594918A Parallel computer system providing multi-ported intelligent memory 失效
标题翻译：并行计算机系统提供多端口智能存储器
公开(公告)号：US5594918A
公开(公告)日：1997-01-14
申请号：US412354
申请日：1995-03-28
申请人： Billy J. Knowles , Clive A. Collins , Christine M. Desnoyers , Donald G. Grice , David B. Rolfe
发明人： Billy J. Knowles , Clive A. Collins , Christine M. Desnoyers , Donald G. Grice , David B. Rolfe
IPC分类号： F02B75/02 , G06F9/318 , G06F9/38 , G06F15/173 , G06F13/28 , G06F13/376
CPC分类号： G06F9/30181 , G06F15/17343 , G06F15/17381 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889 , F02B2075/027
摘要： A parallel computer system providing multi-ported intelligent memory is formed of a plurality of nodes or cells interconnected to provide a shared memory with processors of the network and their memory providing the network routing and shared memory. Each of the nodes provides a functional unit with a processor, shared memory, and communication interface. K zipper ports in addition provide a switching function to interconnect the distributed memory and processors providing the shared memory. The resulting multi-ported shared intelligent memory switch can be used to connect (switch) a variety of computer system elements (CSEs) including computers and direct access storage devices (DASDs). The multi-ported intelligent memory shared memory organized into a collection of cells or nodes and is called the hedgehog. Each node comprises a finite computer memory, a processing unit, and communication interface and at least K of the nodes of the device have a zipper port. The computing system element combines the characteristics of a switch with those of a shared memory. In addition, objects in the shared memory can change state without the intervention of computing system elements (CSEs) that are interconnected to the device (CSE and port) which is a hedgehog switch. A zipper and ISA architecture for the chip are described for implementation of the zipper node of the shared memory device.
摘要翻译：提供多端口智能存储器的并行计算机系统由互连的多个节点或小区形成，以向共享存储器提供网络的处理器及其存储器，以提供网络路由和共享存储器。每个节点提供具有处理器，共享存储器和通信接口的功能单元。 K拉链端口另外提供切换功能，以互连分布式存储器和提供共享存储器的处理器。所产生的多端口共享智能存储交换机可用于连接（切换）各种计算机系统元件（CSE），包括计算机和直接访问存储设备（DASD）。多端口智能存储器共享存储器被组织成一个单元格或节点的集合，被称为刺猬。每个节点包括有限计算机存储器，处理单元和通信接口，并且设备的至少K个节点具有拉链端口。计算系统元件将开关的特性与共享存储器的特性相结合。此外，共享存储器中的对象可以改变状态，而不需要与作为刺猬开关的设备（CSE和端口）互连的计算系统元件（CSE）的干预。描述了用于芯片的拉链和ISA架构，用于实现共享存储器件的拉链节点。

2. 发明授权

US5555528A Dynamic random access memory persistent page implemented as processor register sets 失效
公开(公告)号：US5555528A
公开(公告)日：1996-09-10
申请号：US450324
申请日：1995-05-25
申请人： Clive A. Collins , Billy J. Knowles , Christine M. Desnoyers , David B. Rolfe , Dale E. Pontius
发明人： Clive A. Collins , Billy J. Knowles , Christine M. Desnoyers , David B. Rolfe , Dale E. Pontius
IPC分类号： G11C11/401 , G06F1/32 , G06F12/02 , G06F12/08 , G11C5/14 , G11C7/00 , G11C7/10 , G11C11/4096
CPC分类号： G06F1/3275 , G06F1/32 , G06F12/0215 , G06F12/0882 , G06F12/0893 , G11C11/4096 , G11C7/1051 , G11C7/1078 , Y02B60/1225 , Y02B60/1228
摘要： The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.

3. 发明授权

US5508968A Dynamic random access memory persistent page implemented as processor register sets 失效
标题翻译：作为处理器寄存器集实现的动态随机存取存储器持久页面
公开(公告)号：US5508968A
公开(公告)日：1996-04-16
申请号：US289149
申请日：1994-08-12
申请人： Clive A. Collins , Billy J. Knowles , Christine M. Desnoyers , David B. Rolfe , Dale E. Pontius
发明人： Clive A. Collins , Billy J. Knowles , Christine M. Desnoyers , David B. Rolfe , Dale E. Pontius
IPC分类号： G11C11/401 , G06F1/32 , G06F12/02 , G06F12/08 , G11C5/14 , G11C7/00 , G11C7/10 , G11C11/4096
CPC分类号： G06F1/3275 , G06F1/32 , G06F12/0215 , G06F12/0882 , G06F12/0893 , G11C11/4096 , G11C7/1051 , G11C7/1078 , Y02B60/1225 , Y02B60/1228
摘要： The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.
摘要翻译：使用位于具有处理器的半导体芯片上的动态随机存取存储器（DRAM）的阵列的读出放大器寄存器（SAR）全部保持为全功率，而不可用的阵列被掉电以节省功率。 DRAM的访问电路允许处理器访问每个SAR的字长段彼此独立，使得SAR用作处理器的读/写高速缓存。

4. 发明授权

US5519664A Dynamic random access memory persistent page implemented as processor register sets 失效
公开(公告)号：US5519664A
公开(公告)日：1996-05-21
申请号：US450325
申请日：1995-05-25
申请人： Clive A. Collins , Billy J. Knowles , Christine M. Desnoyers , David B. Rolfe , Dale E. Pontius
发明人： Clive A. Collins , Billy J. Knowles , Christine M. Desnoyers , David B. Rolfe , Dale E. Pontius
IPC分类号： G11C11/401 , G06F1/32 , G06F12/02 , G06F12/08 , G11C5/14 , G11C7/00 , G11C7/10 , G11C11/4096
CPC分类号： G06F1/3275 , G06F1/32 , G06F12/0215 , G06F12/0882 , G06F12/0893 , G11C11/4096 , G11C7/1051 , G11C7/1078 , Y02B60/1225 , Y02B60/1228
摘要： The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.

5. 发明授权

US5590345A Advanced parallel array processor(APAP) 失效
标题翻译：高级并行阵列处理器（APAP）
公开(公告)号：US5590345A
公开(公告)日：1996-12-31
申请号：US887630
申请日：1992-05-22
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Peter M. Kogge , David C. Kuchinski , Billy J. Knowles , Donald M. Lesmeister , Richard E. Miles , Richard E. Nier , Eric E. Retter , Robert R. Richardson , David B. Rolfe , Nicholas J. Schoonover , Vincent J. Smoral , James R. Stupp , Paul A. Wilkinson
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Peter M. Kogge , David C. Kuchinski , Billy J. Knowles , Donald M. Lesmeister , Richard E. Miles , Richard E. Nier , Eric E. Retter , Robert R. Richardson , David B. Rolfe , Nicholas J. Schoonover , Vincent J. Smoral , James R. Stupp , Paul A. Wilkinson
IPC分类号： F02B75/02 , G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F7/483 , G06F15/17337 , G06F15/17343 , G06F15/17368 , G06F15/17381 , G06F15/8007 , G06F15/8015 , G06F15/803 , G06F15/8092 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/3834 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , F02B2075/027
摘要： A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.
摘要翻译：一种具有多个处理器和存储器的计算机系统，所述存储器包括具有多个相似处理器存储器元件的多个可伸缩节点。每个处理器存储器元件具有用于在节点内与节点内的其它类似处理器存储器元件通信的多个通信路径。每个处理器存储器元件还具有用于将节点外部通信到另一个类似计算机系统的可伸缩节点的通信路径。

6. 发明授权

US5617577A Advanced parallel array processor I/O connection 失效
标题翻译：高级并行阵列处理器I / O连接
公开(公告)号：US5617577A
公开(公告)日：1997-04-01
申请号：US400687
申请日：1995-03-08
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , David B. Rolfe , Vincent J. Smoral
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , David B. Rolfe , Vincent J. Smoral
IPC分类号： G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F7/483 , G06F15/17337 , G06F15/17343 , G06F15/17381 , G06F15/8007
摘要： A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper.Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge. Data passes into the network or out of the network through the edge when it is active, and the coupling permits dispersal of data entering the network or collection of data leaving the network such that the data rate through the edge matches both the sustained and peak data rates of the system external to the network.
摘要翻译：多PME计算机系统的快速I / O提供了一种方法，可以将网络耦合到备用网络耦合中。系统耦合称为拉链。我们的I / O拉链概念可用于实现端口到节点中的端口可以由节点驱动的端口或来自系统总线的数据的概念。相反，放出节点的数据对于另一个节点和系统总线的输入将是可用的。将数据输出到系统总线和另一个节点都不是同时进行，而是在不同的周期内完成。拉链将数据传入和传出互连节点的网络用于网状互连节点的系统，包裹圆环的环。使得网络没有边缘，拉链机构沿着与环正交的尺寸逻辑地断开环，使得建立到网络的边缘。耦合动态地在无边缘的网络和具有边缘的网络之间切换网络。当数据有效时，数据通过边缘进入网络或网络，并且耦合允许分散进入网络的数据或离开网络的数据收集，使得通过边缘的数据速率与持续和峰值数据匹配网络外部系统的速率。

7. 发明授权

US5588152A Advanced parallel processor including advanced support hardware 失效
公开(公告)号：US5588152A
公开(公告)日：1996-12-24
申请号：US519859
申请日：1995-08-25
申请人： Michael C. Dapp , Thomas N. Barker , James W. Dieffenderfer , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , David B. Rolfe , Vincent J. Smoral
发明人： Michael C. Dapp , Thomas N. Barker , James W. Dieffenderfer , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , David B. Rolfe , Vincent J. Smoral
IPC分类号： F02B75/02 , G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80
CPC分类号： G06F9/3889 , G06F15/17337 , G06F15/17343 , G06F15/17368 , G06F15/17381 , G06F15/8007 , G06F15/8015 , G06F15/803 , G06F7/483 , G06F9/30 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3891 , F02B2075/027
摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD. MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

8. 发明授权

US5278800A Memory system and unique memory chip allowing island interlace 失效
标题翻译：内存系统和独特的内存芯片允许岛交错
公开(公告)号：US5278800A
公开(公告)日：1994-01-11
申请号：US786139
申请日：1991-10-31
申请人： Warren W. Grunbok , Billy J. Knowles , William R. Milani , Douglas R. Moran , Dale E. Pontius , Donald W. Price , Robert Tamlyn , Yee-Ming Ting , De Tran , Henry Yeh
发明人： Warren W. Grunbok , Billy J. Knowles , William R. Milani , Douglas R. Moran , Dale E. Pontius , Donald W. Price , Robert Tamlyn , Yee-Ming Ting , De Tran , Henry Yeh
IPC分类号： G06F12/06 , G06F13/16 , G11C8/12 , G11C7/00
CPC分类号： G06F12/06 , G06F13/1657 , G11C8/12
摘要： A memory system and a unique memory chip is disclosed wherein multiple islands on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.
摘要翻译：公开了一种存储器系统和独特的存储器芯片，其中芯片上的多个岛可以由单独的岛控制器单独访问，从而可以实现芯片上的多个岛或阵列的并发使用。

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