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1. 发明授权

US5333291A Stride enhancer for high speed memory accesses with line fetching mode and normal mode employing boundary crossing determination 失效
标题翻译：跨线增强器用于线速提取模式的高速存储器存取和采用边界交叉确定的正常模式
公开(公告)号：US5333291A
公开(公告)日：1994-07-26
申请号：US717772
申请日：1991-06-14
申请人： Warren W. Grunbok , Donald W. Price , De Tran
发明人： Warren W. Grunbok , Donald W. Price , De Tran
IPC分类号： G06F9/38 , G06F12/02 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0886 , G06F12/0207 , G06F12/0607
摘要： A stride enhancer provides high memory bandwidth on strides greater than one and minimizes requests to memory. The basic memory module (BSM) design uses line fetches as the basic cache complex fetch mechanism and allows operation of the BSM to be stride independent. In the preferred implementation, the BSM has two fetch modes; a normal mode and a line fetch mode. In the normal mode, a quadword (QW) is fetched as in the conventional design. In the line fetch mode, all double words (DWs) within the referenced line are returned to the storage control element (SCE) at two DWs per cycle for strides one through eight (twice the conventional bandwidth) or at least one DW per cycle for all other strides (equal to the conventional bandwidth). This is accomplished with two DW busses rather than a single QW bus and by interleaving DW storage locations within the BSM. In line fetch mode for strides one through eight, DWs are read out according to the stride on the two DW busses.
摘要翻译：步进增强器在大于1的步幅上提供高存储器带宽，并且最小化对存储器的请求。基本内存模块（BSM）设计使用线取出作为基本缓存复制提取机制，允许BSM独立运行。在优选实现中，BSM具有两种提取模式; 正常模式和线取模式。在正常模式下，如传统设计那样获取四字（QW）。在线取模式下，参考线中的所有双字（DW）将以每个循环两个DW返回到存储控制元件（SCE），以用于步幅1到8（传统带宽的两倍）或每个周期至少一个DW 所有其他步骤（等于传统带宽）。这是通过两个DW总线而不是单个QW总线和通过交织BSM内的DW存储位置来实现的。在一步到八步的直线取出模式下，根据两条DW总线上的步幅读出DW。

2. 发明授权

US5426754A Cross-interrogate method and means for combined scaler and vector processing system 失效
标题翻译：用于组合缩放器和向量处理系统的交叉询问方法和手段
公开(公告)号：US5426754A
公开(公告)日：1995-06-20
申请号：US889022
申请日：1992-05-26
申请人： Donald G. Grice , Donald W. Price , Reza S. Raji
发明人： Donald G. Grice , Donald W. Price , Reza S. Raji
IPC分类号： G06F9/38 , G06F12/08 , G06F15/16 , G06F15/177 , G06F15/78 , G06F17/16 , G06F13/00
CPC分类号： G06F15/8076 , G06F12/0828 , G06F9/3834 , G06F9/3885
摘要： A combined scalar and vector processing system is provided including a scalar XI directory which records the lines currently being stored into by the scalar processors and vector store register devices (VSR) which record lines currently being stored into by vector processors wherein both vector and scalar XI requests are compared to those addresses stored in the vector store register devices. If there is a compare at a VSR, any responses normally provided from the scalar XI directory are held until the vector store register device receives a release signal from the vector processor indicating said vector processor is finished to thereby prevent the scalar processors from fetching invalid data.
摘要翻译：提供了组合的标量和矢量处理系统，其包括标量XI目录，其标记由标量处理器和向量存储寄存器设备（VSR）存储的当前存储的行，其记录当前正被矢量处理器存储的行，其中向量和标量XI 将请求与存储在向量存储寄存器器件中的那些地址进行比较。如果在VSR中存在比较，则保持通常从标量XI目录提供的任何响应，直到向量存储寄存器装置从向量处理器接收到指示所述向量处理器的释放信号完成，从而防止标量处理器取出无效数据。

3. 发明授权

US5265232A Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data 失效
标题翻译：在所选处理器高速缓存中通过数据无效的一致性控制，而无需广播到不具有数据的处理器缓存
公开(公告)号：US5265232A
公开(公告)日：1993-11-23
申请号：US679900
申请日：1991-04-03
申请人： Patrick M. Gannon , Michael Ignatowski , Matthew A. Krygowski , Lishing Liu , Donald W. Price , William K. Rodiger , Gregory Salyer , Yee-Ming Ting , Michael P. Witt
发明人： Patrick M. Gannon , Michael Ignatowski , Matthew A. Krygowski , Lishing Liu , Donald W. Price , William K. Rodiger , Gregory Salyer , Yee-Ming Ting , Michael P. Witt
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/082 , G06F12/0811
摘要： A coherence directory and its methods of operation are disclosed for private processor caches in a multiple processor system to control data coherence in the system. It provides cross-invalidate (XI) controls for the assignment of exclusive and public ownership to data units in the processor caches, including required cross-invalidation of data units among the processor caches to obtain data coherence in the system in an efficient manner. The coherence directory can be used in a multiple processor system with or without any shared second level (L2) cache, shared or private. When a shared L2 cache is used to improve system access time, the coherence directory can also be used as the second level directory for the shared L2 cache and eliminate the need for any additional L2 directory(s).

4. 发明授权

US5418796A Synergistic multiple bit error correction for memory of array chips 失效
标题翻译：用于阵列芯片存储器的协同多位纠错
公开(公告)号：US5418796A
公开(公告)日：1995-05-23
申请号：US675994
申请日：1991-03-26
申请人： Donald W. Price , Yee-Ming Ting
发明人： Donald W. Price , Yee-Ming Ting
IPC分类号： G06F11/10 , G06F12/16 , H03M13/00
CPC分类号： G06F11/1028
摘要： A two-level multiple bit error correction scheme includes at the first level a memory chip with a memory error detection capability that produces a chip error signal (CES) when it detects errors in the bits leaving that chip and at the second level an off-chip ECC facility which interprets generated syndrome bits and chip error signals in order to determine which bits are bad. There are two types of codes distinguished by the absence or presence of parity bits. The use of parity bits allows for the detection of single bit errors in data read from the chip. Therefore, the CES is active only for detected multiple bit errors. Chips not using parity bits are less expensive, but the CES must be active for both single bit and multiple bit errors.
摘要翻译：两级多位错误校正方案在第一级包括具有存储器错误检测能力的存储器芯片，当存储器芯片检测到离开该芯片的位中的错误并且在第二级处产生偏移信号时产生芯片误差信号（CES）芯片ECC设备，其解释生成的校正子位和码片错误信号，以便确定哪些位是坏的。有两种类型的代码是由不存在或存在奇偶校验位来区分的。奇偶校验位的使用允许检测从芯片读取的数据中的单位错误。因此，CES只对检测到的多个位错误有效。不使用奇偶校验位的芯片成本较低，但CES必须对单位和多位错误都有效。

5. 发明授权

US5371893A Look-ahead priority arbitration system and method 失效
标题翻译：先行优先仲裁系统和方法
公开(公告)号：US5371893A
公开(公告)日：1994-12-06
申请号：US816358
申请日：1991-12-27
申请人： Donald W. Price , Forrest A. Reiley , William K. Rodiger
发明人： Donald W. Price , Forrest A. Reiley , William K. Rodiger
IPC分类号： G06F13/362 , G06F13/368 , G06F13/14
CPC分类号： G06F13/368
摘要： An improved arbitration system is disclosed for arbitrating signals at a plurality of input nodes to output nodes where each input node can access any output node. The system includes a FIFO (first-in-first-out) input queue for each node and means for arbitrating the top of each queue for providing the arbitrated output to a given node and means when the top of the input queue has no request for a given node arbitrating the requests from the next to the top entry of the input queues and providing the data from the next to top entry associated with the arbitrated request to the given node.
摘要翻译：公开了一种改进的仲裁系统，用于对多个输入节点处的信号进行仲裁以输出节点，其中每个输入节点可以访问任何输出节点。该系统包括用于每个节点的FIFO（先进先出）输入队列，以及用于仲裁每个队列的顶部以将仲裁的输出提供给给定节点的装置，并且当输入队列的顶部没有请求时给定节点仲裁来自输入队列的下一个到顶部条目的请求，并将与仲裁请求相关联的下一个顶部条目的数据提供给给定节点。

6. 发明授权

US5278800A Memory system and unique memory chip allowing island interlace 失效
标题翻译：内存系统和独特的内存芯片允许岛交错
公开(公告)号：US5278800A
公开(公告)日：1994-01-11
申请号：US786139
申请日：1991-10-31
申请人： Warren W. Grunbok , Billy J. Knowles , William R. Milani , Douglas R. Moran , Dale E. Pontius , Donald W. Price , Robert Tamlyn , Yee-Ming Ting , De Tran , Henry Yeh
发明人： Warren W. Grunbok , Billy J. Knowles , William R. Milani , Douglas R. Moran , Dale E. Pontius , Donald W. Price , Robert Tamlyn , Yee-Ming Ting , De Tran , Henry Yeh
IPC分类号： G06F12/06 , G06F13/16 , G11C8/12 , G11C7/00
CPC分类号： G06F12/06 , G06F13/1657 , G11C8/12
摘要： A memory system and a unique memory chip is disclosed wherein multiple islands on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.
摘要翻译：公开了一种存储器系统和独特的存储器芯片，其中芯片上的多个岛可以由单独的岛控制器单独访问，从而可以实现芯片上的多个岛或阵列的并发使用。

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