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1. 发明授权

US5590345A Advanced parallel array processor(APAP) 失效
标题翻译：高级并行阵列处理器（APAP）
公开(公告)号：US5590345A
公开(公告)日：1996-12-31
申请号：US887630
申请日：1992-05-22
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Peter M. Kogge , David C. Kuchinski , Billy J. Knowles , Donald M. Lesmeister , Richard E. Miles , Richard E. Nier , Eric E. Retter , Robert R. Richardson , David B. Rolfe , Nicholas J. Schoonover , Vincent J. Smoral , James R. Stupp , Paul A. Wilkinson
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Peter M. Kogge , David C. Kuchinski , Billy J. Knowles , Donald M. Lesmeister , Richard E. Miles , Richard E. Nier , Eric E. Retter , Robert R. Richardson , David B. Rolfe , Nicholas J. Schoonover , Vincent J. Smoral , James R. Stupp , Paul A. Wilkinson
IPC分类号： F02B75/02 , G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F7/483 , G06F15/17337 , G06F15/17343 , G06F15/17368 , G06F15/17381 , G06F15/8007 , G06F15/8015 , G06F15/803 , G06F15/8092 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/3834 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , F02B2075/027
摘要： A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.
摘要翻译：一种具有多个处理器和存储器的计算机系统，所述存储器包括具有多个相似处理器存储器元件的多个可伸缩节点。每个处理器存储器元件具有用于在节点内与节点内的其它类似处理器存储器元件通信的多个通信路径。每个处理器存储器元件还具有用于将节点外部通信到另一个类似计算机系统的可伸缩节点的通信路径。

2. 发明授权

US5617577A Advanced parallel array processor I/O connection 失效
标题翻译：高级并行阵列处理器I / O连接
公开(公告)号：US5617577A
公开(公告)日：1997-04-01
申请号：US400687
申请日：1995-03-08
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , David B. Rolfe , Vincent J. Smoral
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , David B. Rolfe , Vincent J. Smoral
IPC分类号： G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F7/483 , G06F15/17337 , G06F15/17343 , G06F15/17381 , G06F15/8007
摘要： A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper.Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge. Data passes into the network or out of the network through the edge when it is active, and the coupling permits dispersal of data entering the network or collection of data leaving the network such that the data rate through the edge matches both the sustained and peak data rates of the system external to the network.
摘要翻译：多PME计算机系统的快速I / O提供了一种方法，可以将网络耦合到备用网络耦合中。系统耦合称为拉链。我们的I / O拉链概念可用于实现端口到节点中的端口可以由节点驱动的端口或来自系统总线的数据的概念。相反，放出节点的数据对于另一个节点和系统总线的输入将是可用的。将数据输出到系统总线和另一个节点都不是同时进行，而是在不同的周期内完成。拉链将数据传入和传出互连节点的网络用于网状互连节点的系统，包裹圆环的环。使得网络没有边缘，拉链机构沿着与环正交的尺寸逻辑地断开环，使得建立到网络的边缘。耦合动态地在无边缘的网络和具有边缘的网络之间切换网络。当数据有效时，数据通过边缘进入网络或网络，并且耦合允许分散进入网络的数据或离开网络的数据收集，使得通过边缘的数据速率与持续和峰值数据匹配网络外部系统的速率。

3. 发明授权

US5625836A SIMD/MIMD processing memory element (PME) 失效
公开(公告)号：US5625836A
公开(公告)日：1997-04-29
申请号：US459374
申请日：1995-06-02
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , Robert R. Richardson , Vincent J. Smoral
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , Robert R. Richardson , Vincent J. Smoral
IPC分类号： G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F15/16
CPC分类号： G06F15/17337 , G06F15/17343 , G06F15/17368 , G06F15/17381 , G06F15/8007 , G06F15/803 , G06F7/483 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

4. 发明授权

US5588152A Advanced parallel processor including advanced support hardware 失效
公开(公告)号：US5588152A
公开(公告)日：1996-12-24
申请号：US519859
申请日：1995-08-25
申请人： Michael C. Dapp , Thomas N. Barker , James W. Dieffenderfer , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , David B. Rolfe , Vincent J. Smoral
发明人： Michael C. Dapp , Thomas N. Barker , James W. Dieffenderfer , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , David B. Rolfe , Vincent J. Smoral
IPC分类号： F02B75/02 , G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80
CPC分类号： G06F9/3889 , G06F15/17337 , G06F15/17343 , G06F15/17368 , G06F15/17381 , G06F15/8007 , G06F15/8015 , G06F15/803 , G06F7/483 , G06F9/30 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3891 , F02B2075/027
摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD. MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

5. 发明授权

US5444705A Dual priority switching apparatus for simplex networks 失效
标题翻译：用于单工网络的双重优先切换装置
公开(公告)号：US5444705A
公开(公告)日：1995-08-22
申请号：US800652
申请日：1991-11-27
申请人： Howard T. Olnowich , Thomas N. Barker , Peter M. Kogge , Gilbert C. Vandling, III
发明人： Howard T. Olnowich , Thomas N. Barker , Peter M. Kogge , Gilbert C. Vandling, III
IPC分类号： G06F11/26 , G06F13/364 , G06F13/40 , G06F15/173 , H03M9/00 , H04L1/00 , H04L7/033 , H04L7/04 , H04L12/18 , H04L12/56 , H04Q11/00 , H04Q11/04 , H04J3/02
CPC分类号： H04L1/0057 , G06F13/364 , G06F13/4022 , G06F15/17375 , G06F15/17393 , H03M9/00 , H04L49/205 , H04L7/0338 , H04L7/044 , H04Q11/0478 , G06F11/261 , H04L49/101 , H04L49/1515 , H04L49/1523 , H04L49/201 , H04L49/40 , H04L49/55 , H04Q11/0066
摘要： A high priority path is added to the normal low priority path through a multi-stage switching network. The high priority path is established at the quickest possible speed because the high priority command is stored at the switch stage involved and made on a priority basis as soon as an output port becomes available. In addition, a positive feedback is given to the node establishing the connection immediately upon the making of the connection so that it may proceed at the earliest possible moment. The high priority path is capable of processing multiple high priority pending requests, and resolving the high priority contention using a snapshot register which implements a rotating priority such that no one requesting device can ever be locked out or experience data starvation. A dual priority switching apparatus with input port connections to output port connections uses as asynchronous means to resolve contention under low priority and the absence of blockage conditions, and switches automatically to a priority driven synchronous means of resolving contention. The protocol requires several parallel data lines plus four control lines so that the switching apparatus can be used for networks having a plurality of nodes, each node having a plurality of input and output ports, with a multiplexer control circuit for each output port for connecting any of I inputs to any of Z outputs, where I and Z can assume any unique value greater or equal to two. The switch has a single physical network path element over which either a low priority or high priority path can be established.
摘要翻译：通过多级交换网络将高优先级路径添加到正常的低优先级路径。高优先级路径以最快的速度建立，因为高优先级命令存储在所涉及的切换阶段，并且一旦输出端口变得可用就在优先级基础上进行。另外，在建立连接时立即建立连接的节点，使得它可以在尽可能早的时刻进行肯定的反馈。高优先级路径能够处理多个高优先级待处理请求，并且使用实现旋转优先级的快照寄存器来解决高优先权争用，使得没有一个请求设备可以被锁定或经历数据不足。具有与输出端口连接的输入端口连接的双重优先级交换设备使用作为异步方式来在低优先级和无阻塞条件下解决争用，并且自动切换到解决争用的优先级驱动的同步装置。该协议需要几条并行数据线加上四条控制线，使得交换设备可用于具有多个节点的网络，每个节点具有多个输入和输出端口，每个输出端口具有多路复用器控制电路，用于连接任何的I输入到任何Z输出，其中I和Z可以采用大于或等于2的任何唯一值。交换机具有单个物理网络路径元素，通过该单个物理网络路径元素可以建立低优先级或高优先级路径。

6. 发明授权

US07788668B2 System and method for implementing distributed priority inheritance 有权
标题翻译：实现分布式优先级继承的系统和方法
公开(公告)号：US07788668B2
公开(公告)日：2010-08-31
申请号：US11148329
申请日：2005-06-09
申请人： Thomas N. Barker
发明人： Thomas N. Barker
IPC分类号： G06F9/46
CPC分类号： G06F9/4887 , G06F9/526
摘要： Priority inheritance is implemented across a distributed system, preferably by use of a mutual exclusion object, referred to as a pseudo-mutex, which provides operations for communicating priority of a task which is held to a different connected processor or node of a network and generating a dummy local command of priority at least equal to that of the held task at the remote processor or node in collaboration with a real-time operating system and middleware. The remote real time operating system then carries out priority inheritance in the normal manner to raise the priority of a blocked task, thus reversing any preemption of that task at the remote processor or node. The increase in priority avoids preemption of lower priority processes and thus increases the execution speed of the executing thread to release the existing lock at an earlier time; allowing a lock to be obtained by the higher priority thread. The middleware serves as an intermediary, communicating messages that include pseudo-mutex arguments or similar communications and requests for enabling priority inheritance across nodes.
摘要翻译：优先级继承是通过分布式系统实现的，优选地通过使用被称为伪互斥体的互斥对象来实现，所述对互斥体提供用于传送被保持到网络的不同连接的处理器或节点的任务的优先级的操作，并产生与实时操作系统和中间件协作，至少等于远程处理器或节点处的任务的至少等同于优先级的虚拟本地命令。然后，远程实时操作系统以正常方式执行优先级继承，以提高被阻塞任务的优先级，从而在远程处理器或节点处逆转该任务的任何抢占。优先级的增加避免了较低优先级进程的抢占，从而提高执行线程在较早时间释放现有锁的执行速度; 允许通过较高优先级线程获得锁。中间件作为中间件，传达包含伪互斥参数或类似通信的消息，以及跨节点启用优先级继承的请求。

7. 发明授权

US5406289A Method and system for tracking multiple regional objects 失效
标题翻译：跟踪多个区域对象的方法和系统
公开(公告)号：US5406289A
公开(公告)日：1995-04-11
申请号：US171327
申请日：1993-12-21
申请人： Thomas N. Barker , Joseph A. Persichetti , Aubrey B. Poore, Jr. , Nenad Rijavec
发明人： Thomas N. Barker , Joseph A. Persichetti , Aubrey B. Poore, Jr. , Nenad Rijavec
IPC分类号： G01S13/72 , G01S13/00
CPC分类号： G01S13/723
摘要： A method for tracking objects is disclosed. First a region containing the objects is scanned to generate a multiplicity of sequential images or data sets of the region. A plurality of points in each of the images or data sets corresponds to a respective plurality of the objects. Next, respective figures of merit are determined for assigning the points to the tracks. Next, a k-dimensional cost function is defined which sums the figures of merit for combinations of assignments from the images or data sets. Next, the complexity of the cost function is reduced by Lagrangian Relaxation by permitting a point to be assigned to more than one track and adding a penalty factor to the cost function when a point is assigned to more than one track. The reducing step is iteratively repeated and the resultant penalized cost function is solved. Next, an auxiliary function at a (k-1)-dimension is defined as a function of lower order penalty factors and a solution at the dimension at which the penalized cost function was solved directly. Next, a gradient of the auxiliary function is determined, a step is made in the direction of the gradient to identify a peak region of the auxiliary function and penalty factors at the peak region are determined. The penalty factors at the peak region are used to determine track assignments for the points in the images or data sets. Then one or more of the following actions are taken based on the track assignments: sending a warning to aircraft or a ground or sea facility, controlling air traffic, controlling anti-aircraft or anti-missile equipment, taking evasive action, working on one of the objects.
摘要翻译：公开了一种跟踪对象的方法。首先，扫描包含对象的区域以生成该区域的多个连续图像或数据集。每个图像或数据集中的多个点对应于相应的多个对象。接下来，确定各个品质因数以将点分配给轨道。接下来，定义k维成本函数，其与图像或数据集的分配组合的总和值相加。接下来，通过拉格朗日松弛减少成本函数的复杂度，通过允许将点分配给多于一个轨道，并且当点被分配给多于一个轨道时，将成本函数添加惩罚因子。迭代地重复还原步骤，并且解决所得的惩罚成本函数。接下来，在（k-1）维度处的辅助函数被定义为低阶惩罚因子的函数，并且在惩罚成本函数直接求解的维度处求解。接下来，确定辅助功能的梯度，在梯度方向上进行步骤以识别辅助功能的峰值区域，并且确定峰值区域的惩罚因子。峰值区域的惩罚因子用于确定图像或数据集中的点的轨道分配。然后根据轨道分配采取以下一项或多项行动：向飞机或地面或海上设施发出警告，控制空中交通，控制高空或反导弹设备，采取回避措施，在对象。

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