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1. 发明授权

US5617577A Advanced parallel array processor I/O connection 失效
标题翻译：高级并行阵列处理器I / O连接
公开(公告)号：US5617577A
公开(公告)日：1997-04-01
申请号：US400687
申请日：1995-03-08
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , David B. Rolfe , Vincent J. Smoral
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , David B. Rolfe , Vincent J. Smoral
IPC分类号： G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F7/483 , G06F15/17337 , G06F15/17343 , G06F15/17381 , G06F15/8007
摘要： A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper.Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge. Data passes into the network or out of the network through the edge when it is active, and the coupling permits dispersal of data entering the network or collection of data leaving the network such that the data rate through the edge matches both the sustained and peak data rates of the system external to the network.
摘要翻译：多PME计算机系统的快速I / O提供了一种方法，可以将网络耦合到备用网络耦合中。系统耦合称为拉链。我们的I / O拉链概念可用于实现端口到节点中的端口可以由节点驱动的端口或来自系统总线的数据的概念。相反，放出节点的数据对于另一个节点和系统总线的输入将是可用的。将数据输出到系统总线和另一个节点都不是同时进行，而是在不同的周期内完成。拉链将数据传入和传出互连节点的网络用于网状互连节点的系统，包裹圆环的环。使得网络没有边缘，拉链机构沿着与环正交的尺寸逻辑地断开环，使得建立到网络的边缘。耦合动态地在无边缘的网络和具有边缘的网络之间切换网络。当数据有效时，数据通过边缘进入网络或网络，并且耦合允许分散进入网络的数据或离开网络的数据收集，使得通过边缘的数据速率与持续和峰值数据匹配网络外部系统的速率。

2. 发明授权

US5588152A Advanced parallel processor including advanced support hardware 失效
公开(公告)号：US5588152A
公开(公告)日：1996-12-24
申请号：US519859
申请日：1995-08-25
申请人： Michael C. Dapp , Thomas N. Barker , James W. Dieffenderfer , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , David B. Rolfe , Vincent J. Smoral
发明人： Michael C. Dapp , Thomas N. Barker , James W. Dieffenderfer , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , David B. Rolfe , Vincent J. Smoral
IPC分类号： F02B75/02 , G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80
CPC分类号： G06F9/3889 , G06F15/17337 , G06F15/17343 , G06F15/17368 , G06F15/17381 , G06F15/8007 , G06F15/8015 , G06F15/803 , G06F7/483 , G06F9/30 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3891 , F02B2075/027
摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD. MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

3. 发明授权

US5590345A Advanced parallel array processor(APAP) 失效
标题翻译：高级并行阵列处理器（APAP）
公开(公告)号：US5590345A
公开(公告)日：1996-12-31
申请号：US887630
申请日：1992-05-22
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Peter M. Kogge , David C. Kuchinski , Billy J. Knowles , Donald M. Lesmeister , Richard E. Miles , Richard E. Nier , Eric E. Retter , Robert R. Richardson , David B. Rolfe , Nicholas J. Schoonover , Vincent J. Smoral , James R. Stupp , Paul A. Wilkinson
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Peter M. Kogge , David C. Kuchinski , Billy J. Knowles , Donald M. Lesmeister , Richard E. Miles , Richard E. Nier , Eric E. Retter , Robert R. Richardson , David B. Rolfe , Nicholas J. Schoonover , Vincent J. Smoral , James R. Stupp , Paul A. Wilkinson
IPC分类号： F02B75/02 , G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F7/483 , G06F15/17337 , G06F15/17343 , G06F15/17368 , G06F15/17381 , G06F15/8007 , G06F15/8015 , G06F15/803 , G06F15/8092 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/3834 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , F02B2075/027
摘要： A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.
摘要翻译：一种具有多个处理器和存储器的计算机系统，所述存储器包括具有多个相似处理器存储器元件的多个可伸缩节点。每个处理器存储器元件具有用于在节点内与节点内的其它类似处理器存储器元件通信的多个通信路径。每个处理器存储器元件还具有用于将节点外部通信到另一个类似计算机系统的可伸缩节点的通信路径。

4. 发明授权

US5625836A SIMD/MIMD processing memory element (PME) 失效
公开(公告)号：US5625836A
公开(公告)日：1997-04-29
申请号：US459374
申请日：1995-06-02
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , Robert R. Richardson , Vincent J. Smoral
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , Robert R. Richardson , Vincent J. Smoral
IPC分类号： G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F15/16
CPC分类号： G06F15/17337 , G06F15/17343 , G06F15/17368 , G06F15/17381 , G06F15/8007 , G06F15/803 , G06F7/483 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

5. 发明申请

US20080209560A1 Active intrusion resistant environment of layered object and compartment key (airelock) 审中-公开
标题翻译：分层物体和隔间钥匙（airelock）的主动入侵防护环境
公开(公告)号：US20080209560A1
公开(公告)日：2008-08-28
申请号：US11798580
申请日：2007-05-15
申请人： Michael C. Dapp
发明人： Michael C. Dapp
IPC分类号： G08B23/00 , G06F15/173 , G06F11/20 , H04L9/00
CPC分类号： H04L63/1416 , H04L63/20
摘要： A secure infrastructure system and method with user transparent signaling for communicating detection of signals at a network node having characteristics of a potential attack and for controlling communications at a node from another node in response to the user transparent signals. A processor is connected to routers and the network through an encryption engine and includes a manager object to issue control commands to nodes of a locally lower hierarchical tier and managed objects to detect potential attacks and exercise control over the routers responsive to signals from a node of a locally higher hierarchical tier. Faults or potential attacks are compartmentalized to a node or sector of the network and isolated while normal communications are continued over redundant network links.
摘要翻译：一种具有用户透明信令的安全基础设施系统和方法，用于在具有潜在攻击特征的网络节点处传送信号检测，并响应于用户透明信号控制来自另一节点的节点上的通信。处理器通过加密引擎连接到路由器和网络，并且包括管理对象，以向本地较低分级层的节点发出控制命令，并且管理对象以响应于来自节点的信号来检测潜在的攻击和对路由器进行控制本地较高的层级。故障或潜在攻击分隔成网络的一个节点或扇区，并在通过冗余网络链路进行正常通信时隔离。

6. 发明申请

US20110162063A1 METHODS AND APPARATUS FOR PROVIDING ACCESS TO VEHICLE ELECTRONIC SYSTEMS 有权
标题翻译：用于提供车辆电子系统的方法和装置
公开(公告)号：US20110162063A1
公开(公告)日：2011-06-30
申请号：US13042669
申请日：2011-03-08
申请人： Kenneth B. Donovan , Michael C. Dapp , Jeremy Impson , John Moody
发明人： Kenneth B. Donovan , Michael C. Dapp , Jeremy Impson , John Moody
IPC分类号： G06F21/00
CPC分类号： H04L67/125
摘要： One embodiment is directed to providing access between external systems and embedded vehicle electronic systems. That is, an interface module may receive information from a system external to the vehicle, determine an embedded system of the vehicle to which to provide the information, and provide the information to the embedded system. Similarly, the interface module may receive information a embedded electronic systems of a vehicle, determine a system external the vehicle to which to provide the information, and provide the information to the external system.
摘要翻译：一个实施例旨在提供外部系统和嵌入式车载电子系统之间的接入。也就是说，接口模块可以从车辆外部的系统接收信息，确定要向其提供信息的车辆的嵌入式系统，并将信息提供给嵌入式系统。类似地，接口模块可以接收车辆的嵌入式电子系统的信息，确定向其提供信息的车辆外部的系统，并将信息提供给外部系统。

7. 发明授权

US07225467B2 Active intrusion resistant environment of layered object and compartment keys (airelock) 有权
标题翻译：分层物体和隔间钥匙（airelock）的主动入侵防护环境
公开(公告)号：US07225467B2
公开(公告)日：2007-05-29
申请号：US09973769
申请日：2001-10-11
申请人： Michael C. Dapp
发明人： Michael C. Dapp
IPC分类号： G08B23/00 , G06F11/20 , G06B15/173 , H04L9/00
CPC分类号： H04L63/1416 , H04L63/20
摘要： A high level of security and fault tolerance is provided in a digital network by use of highly secure infrastructure of user transparent signalling for communicating detection of signals at a network node having characteristics of a potential attack to another node and controlling communications at routers at the node from another node in response to the user transparent signals. A processor is connected to the routers and the network through an encryption engine and includes a manager object to issue control commands to nodes of a locally lower hierarchy tier and managed objects to detect potential attacks and exercise control over the routers responsive to signals from a node of a locally higher hierarchy tier. Identifications are provided for communications between nodes regardless of whether or not a corresponding user is identified and communications are logged. Thus any network session comprises one or more secure sessions in a plurality of security domains and any fault or potential attack can be compartmentalized to a node or sector of the network and isolated while normal communications are continued over redundant network links.
摘要翻译：通过使用用户透明信令的高度安全的基础设施来提供高水平的安全性和容错性，用于在具有对另一个节点的潜在攻击的特征的网络节点处的信号的检测进行通信，并控制该节点处的路由器的通信从另一个节点响应用户的透明信号。处理器通过加密引擎连接到路由器和网络，并且包括管理对象，以向本地较低层级的节点发出控制命令，并且管理对象以响应于来自节点的信号来检测潜在的攻击和对路由器进行控制的本地较高层级。为节点之间的通信提供标识，而不管相关用户是否被识别，并且记录通信。因此，任何网络会话包括多个安全域中的一个或多个安全会话，并且任何故障或潜在攻击可被划分为网络的节点或扇区，并且在通过冗余网络链路继续正常通信时被隔离。

8. 发明授权

US08214102B2 Methods and apparatus for providing access to vehicle electronic systems 有权
标题翻译：用于提供对车载电子系统的访问的方法和装置
公开(公告)号：US08214102B2
公开(公告)日：2012-07-03
申请号：US13042669
申请日：2011-03-08
申请人： Kenneth B. Donovan , Michael C. Dapp , Jeremy Impson , John Moody
发明人： Kenneth B. Donovan , Michael C. Dapp , Jeremy Impson , John Moody
IPC分类号： G06F19/00
CPC分类号： H04L67/125
摘要： One embodiment is directed to providing access between external systems and embedded vehicle electronic systems. That is, an interface module may receive information from a system external to the vehicle, determine an embedded system of the vehicle to which to provide the information, and provide the information to the embedded system. Similarly, the interface module may receive information a embedded electronic systems of a vehicle, determine a system external the vehicle to which to provide the information, and provide the information to the external system.
摘要翻译：一个实施例旨在提供外部系统和嵌入式车载电子系统之间的接入。也就是说，接口模块可以从车辆外部的系统接收信息，确定要向其提供信息的车辆的嵌入式系统，并将信息提供给嵌入式系统。类似地，接口模块可以接收车辆的嵌入式电子系统的信息，确定向其提供信息的车辆外部的系统，并将信息提供给外部系统。

9. 发明申请

US20080120366A1 Methods and apparatus for providing access to vehicle electronic systems 有权
标题翻译：用于提供对车载电子系统的访问的方法和装置
公开(公告)号：US20080120366A1
公开(公告)日：2008-05-22
申请号：US11603327
申请日：2006-11-21
申请人： Kenneth B. Donovan , Michael C. Dapp , Jeremy Impson , John Moody
发明人： Kenneth B. Donovan , Michael C. Dapp , Jeremy Impson , John Moody
IPC分类号： G06F15/16
CPC分类号： H04L67/125
摘要： One embodiment is directed to providing access between external systems and embedded vehicle electronic systems. That is, an interface module may receive information from a system external to the vehicle, determine an embedded system of the vehicle to which to provide the information, and provide the information to the embedded system. Similarly, the interface module may receive information a embedded electronic systems of a vehicle, determine a system external the vehicle to which to provide the information, and provide the information to the external system.
摘要翻译：一个实施例旨在提供外部系统和嵌入式车载电子系统之间的接入。也就是说，接口模块可以从车辆外部的系统接收信息，确定要向其提供信息的车辆的嵌入式系统，并将信息提供给嵌入式系统。类似地，接口模块可以接收车辆的嵌入式电子系统的信息，确定向其提供信息的车辆外部的系统，并将信息提供给外部系统。

10. 发明授权

US07213265B2 Real time active network compartmentalization 有权
标题翻译：实时活动网络划分
公开(公告)号：US07213265B2
公开(公告)日：2007-05-01
申请号：US09973776
申请日：2001-10-11
申请人： Michael C. Dapp
发明人： Michael C. Dapp
IPC分类号： G06F11/34 , G06F15/173 , H04L12/26 , G08B23/00
CPC分类号： H04L63/0272 , G06F11/1482 , H04L63/1458
摘要： Security policy manager devices are leveraged by manager objects to use highly secure user transparent communications to provide detection of questionable activities at every node, automatic collection of information related to any potential attack, isolation of the offending object with arbitrary flexibility of response (e.g. flexibly determining the level of certainty of an attack for initiation of a response in accordance with the number of nodes to be partitioned that is determined by the collected data concerning the potential attack), changing trust relationships between security domains, limiting the attack and launching offensive information warfare capabilities (e.g. outbound from the compromised node while limiting or eliminating inbound communications) in log time and simultaneously and/or concurrently in different but possibly overlapping sections or segments of a digital network of arbitrary configuration.
摘要翻译：安全策略管理器设备由管理对象利用，使用高度安全的用户透明通信来提供对每个节点的可疑活动的检测，自动收集与任何潜在攻击相关的信息，以任意的响应灵活性隔离违规对象（例如灵活地确定根据收集的有关潜在攻击的数据确定的要分区的节点数，启动响应的攻击的确定性级别），改变安全域之间的信任关系，限制攻击和发起攻击性信息战功能（例如，在受限的节点中出站，同时限制或消除入站通信），同时和/或并发在任意配置的数字网络的不同但可能重叠的部分或多个段中。

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