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1. 发明授权

US07203127B1 Apparatus and method for dynamically controlling data transfer in memory device 有权
标题翻译：用于动态控制存储器件中的数据传输的装置和方法
公开(公告)号：US07203127B1
公开(公告)日：2007-04-10
申请号：US11241601
申请日：2005-09-29
申请人： Robert Tamlyn , Joshua Osborne
发明人： Robert Tamlyn , Joshua Osborne
IPC分类号： G11C8/00
CPC分类号： G11C7/08 , G11C11/4091
摘要： Methods and apparatus for operating a secondary sense amplifier according to different timings. Embodiments of the invention generally provide a secondary sense amplifier configured to dynamically adjust its timing according to a need for data in an output buffer. In one embodiment, the secondary sense amplifier is set (causing data to be driven out) by a signal, SSA_SET, the timing of which is adjusted on the basis of a predefined delay and a need for data at the output buffer.
摘要翻译：根据不同时序操作次级放大器的方法和装置。本发明的实施例通常提供一个次级感测放大器，其被配置为根据对输出缓冲器中的数据的需要来动态调整其定时。在一个实施例中，通过信号SSA_SET来设置辅助感测放大器（使数据被驱出），SSA_SET的定时基于预定义的延迟和对输出缓冲器的数据的需要进行调整。

2. 发明授权

US5901093A Redundancy architecture and method for block write access cycles permitting defective memory line replacement 失效
标题翻译：用于块写访问周期的冗余架构和方法允许有缺陷的存储器线更换
公开(公告)号：US5901093A
公开(公告)日：1999-05-04
申请号：US464044
申请日：1995-06-05
申请人： Nathan Rafael Hiltebeitel , Robert Tamlyn , Steven William Tomashot , Thomas Walter Wyckoff
发明人： Nathan Rafael Hiltebeitel , Robert Tamlyn , Steven William Tomashot , Thomas Walter Wyckoff
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/808 , G11C29/818
摘要： An invention is disclosed which implements bit line redundancy in a memory module, such as a dynamic random access memory (DRAM), in accordance with a block write operation. The block write operation is commonly used in dual port RAMs, sometimes referred to as video random access memories (VRAM). Specifically, a block write operation allows a plurality of bits of data to be written to a plurality of adjacent bit lines defined by a column address. The precise combination of adjacent bit lines selected by the column address is designated by an address mask. The invention provides a memory module with a redundant bit decoder that incorporates an address masking function into the redundant bit decoder during block write operations and also bypasses a masking function during normal read and write operations. This redundant bit decoder allows a single redundant bit line to replace any single defective bit line of the selected group of block write bit lines. It eliminates the need for replacing all the selected bit lines and, thereby, saves silicon area and maximizes the utilization of available redundant bit elements.
摘要翻译：公开了根据块写入操作在存储器模块（例如动态随机存取存储器（DRAM））中实现位线冗余的发明。块写操作通常用于双端口RAM，有时称为视频随机存取存储器（VRAM）。具体地，块写入操作允许将多个数据位写入由列地址定义的多个相邻位线。由列地址选择的相邻位线的精确组合由地址掩码指定。本发明提供了一种具有冗余位解码器的存储器模块，其在块写入操作期间将地址掩蔽功能合并到冗余位解码器中，并且在正常读取和写入操作期间绕过掩蔽功能。该冗余位解码器允许单个冗余位线替代所选择的块写入位线组中的任何单个缺陷位线。它不需要更换所有选定的位线，从而节省了硅面积并最大限度地利用了可用的冗余位元件。

3. 发明授权

US5490114A High performance extended data out 失效
标题翻译：高性能扩展数据输出
公开(公告)号：US5490114A
公开(公告)日：1996-02-06
申请号：US362086
申请日：1994-12-22
申请人： Edward Butler , Robert B. Goodwin , Hemen R. Shah , Robert Tamlyn
发明人： Edward Butler , Robert B. Goodwin , Hemen R. Shah , Robert Tamlyn
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1024
摘要： A high performance latch for read and write operations in RAM having a Complimentary Interlock circuit that eliminates the need for external timing to the RAM which might limit its high performance operation. For both read and write operations, the complementary interlock circuit extends a latching signal until valid data appears on the read or write data lines, thus preventing a valid data miss.
摘要翻译：用于具有免费联锁电路的RAM中的读写操作的高性能锁存器，无需外部定时到RAM，这可能限制其高性能操作。对于读和写操作，互补互锁电路扩展了锁存信号，直到有效数据出现在读或写数据线上，从而防止有效的数据丢失。

4. 发明申请

US20070070788A1 APPARATUS AND METHOD FOR DYNAMICALLY CONTROLLING DATA TRANSFER IN MEMORY DEVICE 有权
标题翻译：用于动态地控制存储器件中的数据传输的装置和方法
公开(公告)号：US20070070788A1
公开(公告)日：2007-03-29
申请号：US11241601
申请日：2005-09-29
申请人： Robert Tamlyn , Joshua Osborne
发明人： Robert Tamlyn , Joshua Osborne
IPC分类号： G11C8/00
CPC分类号： G11C7/08 , G11C11/4091
摘要： Methods and apparatus for operating a secondary sense amplifier according to different timings. Embodiments of the invention generally provide a secondary sense amplifier configured to dynamically adjust its timing according to a need for data in an output buffer. In one embodiment, the secondary sense amplifier is set (causing data to be driven out) by a signal, SSA_SET, the timing of which is adjusted on the basis of a predefined delay and a need for data at the output buffer.
摘要翻译：根据不同时序操作次级放大器的方法和装置。本发明的实施例通常提供一个次级感测放大器，其被配置为根据对输出缓冲器中的数据的需要来动态调整其定时。在一个实施例中，通过信号SSA_SET来设置辅助感测放大器（使数据被驱出），SSA_SET的定时基于预定义的延迟和对输出缓冲器的数据的需要进行调整。

5. 发明授权

US5606269A Non-delay based address transition detector (ATD) 失效
标题翻译：基于非延迟的地址转换检测器（ATD）
公开(公告)号：US5606269A
公开(公告)日：1997-02-25
申请号：US548651
申请日：1995-10-26
申请人： Dale E. Pontius , Robert Tamlyn
发明人： Dale E. Pontius , Robert Tamlyn
IPC分类号： H03K5/1534 , H03K19/003
CPC分类号： H03K5/1534
摘要： A circuit for detecting an input signal, the circuit having an input node and an output node, includes a first latch having a set input coupled to the input node, for detecting falling transitions at the input node. A second latch having a set input coupled to the input node, detects rising transitions at the input node. A first logic device, responsive to outputs of the first and second latches, detects that an input signal has been received at both the first and second latches. A second logic device, responsive to a complement output of both the first and second latches, resets both the first and second latches.
摘要翻译：用于检测输入信号的电路，具有输入节点和输出节点的电路包括具有耦合到输入节点的设置输入的第一锁存器，用于检测输入节点处的下降转换。具有耦合到输入节点的设置输入的第二锁存器检测输入节点处的上升转变。响应于第一和第二锁存器的输出的第一逻辑器件检测到在第一和第二锁存器都已经接收到输入信号。响应于第一和第二锁存器的补码输出的第二逻辑器件复位第一和第二锁存器。

6. 发明授权

US08630141B2 Circuits and methods for providing refresh addresses and alternate refresh addresses to be refreshed 有权
标题翻译：用于提供刷新地址和备用刷新地址以刷新的电路和方法
公开(公告)号：US08630141B2
公开(公告)日：2014-01-14
申请号：US13016657
申请日：2011-01-28
申请人： Robert Tamlyn
发明人： Robert Tamlyn
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C8/18 , G11C11/408
摘要： Circuits and refresh address circuits for providing a refresh address, and methods for refreshing memory cells. One such method includes refreshing a first plurality of memory cells and interrupting the refreshing of the first plurality of memory cells. A second plurality of memory cells is refreshed, at least one of the second plurality of memory cells the same as one of the first plurality of memory cells. Refreshing of the first plurality of memory cells is resumed following the refreshing of the second plurality of memory cells. One such refresh address circuit includes a refresh address counter configured to provide addresses to be refreshed and a refresh address interrupt circuit configured to interrupt the provision of addresses. An alternate refresh address circuit is configured to provide an alternate address and the refresh address counter resumes providing the addresses responsive to completing the refreshing of the alternate address.
摘要翻译：用于提供刷新地址的电路和刷新地址电路，以及用于刷新存储器单元的方法。一种这样的方法包括刷新第一多个存储单元并中断第一多个存储单元的刷新。刷新第二多个存储器单元，第二多个存储器单元中的至少一个与第一多个存储器单元中的一个相同。在第二多个存储单元的刷新之后，恢复第一多个存储单元的刷新。一个这样的刷新地址电路包括被配置为提供要刷新的地址的刷新地址计数器和被配置为中断提供地址的刷新地址中断电路。替代刷新地址电路被配置为提供备用地址，并且刷新地址计数器恢复提供响应于完成备用地址的刷新的地址。

7. 发明申请

US20120195149A1 CIRCUITS AND METHODS FOR PROVIDING REFRESH ADDRESSES AND ALTERNATE REFRESH ADDRESSES TO BE REFRESHED 有权
标题翻译：提供刷新地址和替代修复地址的电路和方法要刷新
公开(公告)号：US20120195149A1
公开(公告)日：2012-08-02
申请号：US13016657
申请日：2011-01-28
申请人： Robert Tamlyn
发明人： Robert Tamlyn
IPC分类号： G11C8/04 , G11C8/10 , G11C7/00 , G11C8/12
CPC分类号： G11C11/406 , G11C8/18 , G11C11/408
摘要： Circuits and refresh address circuits for providing a refresh address, and methods for refreshing memory cells. An example method includes refreshing a first plurality of memory cells and interrupting the refreshing of the first plurality of memory cells. A second plurality of memory cells is refreshed, at least one of the second plurality of memory cells the same as one of the first plurality of memory cells. Refreshing of the first plurality of memory cells is resumed following the refreshing of the second plurality of memory cells. An example refresh address circuit includes a refresh address counter configured to provide addresses to be refreshed and a refresh address interrupt circuit configured to interrupt the provision of addresses. An alternate refresh address circuit is configured to provide an alternate address and the refresh address counter resumes providing the addresses responsive to completing the refreshing of the alternate address.
摘要翻译：用于提供刷新地址的电路和刷新地址电路，以及用于刷新存储器单元的方法。示例性方法包括刷新第一多个存储器单元并中断第一多个存储器单元的刷新。刷新第二多个存储器单元，第二多个存储器单元中的至少一个与第一多个存储器单元中的一个相同。在第二多个存储单元的刷新之后，恢复第一多个存储单元的刷新。示例性刷新地址电路包括被配置为提供要刷新的地址的刷新地址计数器和被配置为中断提供地址的刷新地址中断电路。替代刷新地址电路被配置为提供备用地址，并且刷新地址计数器恢复提供响应于完成备用地址的刷新的地址。

8. 发明申请

US20080238483A1 Reduced-Delay Clocked Logic 有权
标题翻译：减少延迟时钟逻辑
公开(公告)号：US20080238483A1
公开(公告)日：2008-10-02
申请号：US11692245
申请日：2007-03-28
申请人： Robert Tamlyn
发明人： Robert Tamlyn
IPC分类号： H03K19/00
CPC分类号： H03K3/03
摘要： Delay in a clocked logic circuit is reduced by partially determining a next state of the clocked logic circuit based on a current state of the clocked logic circuit during a first portion of a clock cycle. The partially determined next state of the clocked logic circuit is prevented from affecting the current state of the clocked logic circuit during the first portion of the clock cycle. The next state of the clocked logic circuit is completely determined based on a previous state of the clocked logic circuit and the partially determined next state of the clocked logic circuit during a second portion of the clock cycle.
摘要翻译：在时钟周期的第一部分期间，基于时钟逻辑电路的当前状态部分地确定时钟逻辑电路的下一个状态来减少时钟逻辑电路的延迟。抑制时钟逻辑电路的部分确定的下一状态在时钟周期的第一部分期间不影响时钟逻辑电路的当前状态。在时钟周期的第二部分期间，基于时钟逻辑电路的先前状态和时钟逻辑电路的部分确定的下一状态，完全确定时钟逻辑电路的下一状态。

9. 发明授权

US06009026A Compressed input/output test mode 失效
标题翻译：压缩输入/输出测试模式
公开(公告)号：US06009026A
公开(公告)日：1999-12-28
申请号：US901509
申请日：1997-07-28
申请人： Robert Tamlyn , Edward Butler
发明人： Robert Tamlyn , Edward Butler
IPC分类号： G11C7/10 , G11C29/28 , G11C29/40 , G11C7/00
CPC分类号： G11C29/28 , G11C29/40 , G11C7/10
摘要： The present invention discloses a system and method of testing semiconductor memory devices formed as integrated circuits on semiconductor substrates. The present invention allows parallel testing of arrays using only one input/output (I/O or DQ) to write to the arrays and only two DQs to read from the arrays. The broad search should be directed to methods of compressing the time and number of I/O's required for testing wide, high pin count, or highly partitioned memory arrays. The specific method of this invention comprises simultaneously writing the same test bit to each array, simultaneously reading a common address from each array and comparing the output of each array to report a fail if all outputs are not the same.
摘要翻译：本发明公开了一种在半导体衬底上形成为集成电路的半导体存储器件的测试系统和方法。本发明允许使用仅一个输入/输出（I / O或DQ）对数组进行并行测试来写入阵列，并且只有两个DQ从阵列读取。广泛的搜索应该针对压缩测试宽，高引脚数或高度分区的存储器阵列所需的I / O的时间和数量的方法。本发明的具体方法包括同时将相同的测试位写入每个阵列，同时从每个阵列读取公共地址，并且如果所有输出不相同，则比较每个阵列的输出以报告失败。

10. 发明授权

US5065368A Video RAM double buffer select control 失效
标题翻译：视频RAM双重缓冲器选择控制
公开(公告)号：US5065368A
公开(公告)日：1991-11-12
申请号：US352442
申请日：1989-05-16
申请人： Satish Gupta , Randall L. Henderson , Nathan R. Hiltebeitel , Robert Tamlyn , Steven W. Tomashot , Todd Williams
发明人： Satish Gupta , Randall L. Henderson , Nathan R. Hiltebeitel , Robert Tamlyn , Steven W. Tomashot , Todd Williams
IPC分类号： G11C11/401 , G11C7/10 , G11C8/00 , G11C11/4096
CPC分类号： G11C11/4096 , G11C7/1075 , G11C8/00
摘要： An implementation of a serial access memory register that facilitates the selecting from two alternate frame buffers on a per pixel basis. The frame buffers are each stored in a portion of a row in a single video RAM. Following data transfer to the serial access memory register, data from each of the two frame buffers is available. A double buffer select signal controls the selection of which half of the serial access memory register will put data on the output bus for each serial clock signal. The serial clock increments the address pointers in both halves of the serial access memory port simultaneously.

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