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1. 发明授权

US4618784A High-performance, high-density CMOS decoder/driver circuit 失效
标题翻译：高性能，高密度CMOS解码器/驱动电路
公开(公告)号：US4618784A
公开(公告)日：1986-10-21
申请号：US695664
申请日：1985-01-28
申请人： Barbara A. Chappell , Thekkemadathil V. Rajeevakumar , Stanley E. Schuster , Lewis M. Terman
发明人： Barbara A. Chappell , Thekkemadathil V. Rajeevakumar , Stanley E. Schuster , Lewis M. Terman
IPC分类号： H03K19/096 , G11C8/10 , G11C11/34 , G11C11/407 , G11C11/413 , G11C8/00 , H03K19/017 , H03K19/20
CPC分类号： G11C8/10
摘要： A decoder/driver circuit for a semiconductor momory having a A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .PHI.PC line is included for receiving a .PHI.PC precharge clock signal thereon and a .PHI.R line is provided for receiving a .PHI.R reset clock signal thereon. The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the AN line is high. A driver circuit is connected to the selection means and is responsive to the output signal of the NOR decoder circuit and the first selection signal to provide an output signal on a first memory word line and is further responsive to the output signal of the NOR decoder circuit and the second selection signal to provide an output signal on a second memory word line.
摘要翻译：一种具有A1至AN（真）和A1至＆amp; upbar和A（补码）地址线的半导体器件的解码器/驱动器电路，用于从内部地址缓冲器向其接收A1至AN地址位信号。包括PHI PC线，用于在其上接收PHI PC预充电时钟信号，并且提供PHI R线用于在其上接收PHI R复位时钟信号。解码器/驱动器电路包括NOR解码器装置，其具有连接到用于AN到AN-1地址位的真和补地址线的A1至AN-1或A1至AN-1的多个晶体管开关装置，用于产生高电平或根据地址位状态在解码器输出节点上的低电平信号。解码器/驱动器电路还包括选择装置，其具有连接到解码器的输出节点的多个晶体管器件，以在解码器输出节点和AN线路为高电平时产生第一选择信号，并且当解码器输出时产生第二选择信号节点和＆upbar＆A线高。驱动器电路连接到选择装置，并且响应于NOR解码器电路的输出信号和第一选择信号，以在第一存储器字线上提供输出信号，并且还响应于NOR解码器电路的输出信号以及第二选择信号，以在第二存储器字线上提供输出信号。

2. 发明授权

US4638462A Self-timed precharge circuit 失效
标题翻译：自定时预充电电路
公开(公告)号：US4638462A
公开(公告)日：1987-01-20
申请号：US696624
申请日：1985-01-31
申请人： Thekkemadathil V. Rajeevakumar , Lewis M. Terman
发明人： Thekkemadathil V. Rajeevakumar , Lewis M. Terman
IPC分类号： G11C11/407 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/18 , G11C11/409 , G11C11/41 , G11C7/00
CPC分类号： G11C7/22 , G11C7/12 , G11C8/08 , G11C8/18
摘要： A self-timed precharge circuit for a memory array consisting of an X-line complement circuit connected to the outputs of a plurality of falling edge detectors, and a precharge generator circuit connected to the output of the X-line complement circuit. Each falling edge detector is connected to a separate wordline (WL, WL+1, . . . WL+N) of the system memory array. In operation, the precharge generator circuit is triggered with a signal on the output lead from a falling edge detector which is activated when the selected wordline (WL, WL+1, . . . WL+N) connected thereto resets.
摘要翻译：一种用于由连接到多个下降沿检测器的输出的X线互补电路组成的存储器阵列的自定时预充电电路和连接到X线互补电路的输出的预充电发生器电路。每个下降沿检测器连接到系统存储器阵列的单独字线（WL，WL + 1，... WL + N）。在操作中，预充电发生器电路由下降沿检测器的输出引线上的信号触发，当与所连接的所选择的字线（WL，WL + 1，...，WL + N）复位时，预激电发生器电路被激活。

3. 发明授权

US4763180A Method and structure for a high density VMOS dynamic ram array 失效
标题翻译：高密度VMOS动态RAM阵列的方法和结构
公开(公告)号：US4763180A
公开(公告)日：1988-08-09
申请号：US945275
申请日：1986-12-22
申请人： Wei Hwang , Stanley E. Schuster , Lewis M. Terman
发明人： Wei Hwang , Stanley E. Schuster , Lewis M. Terman
IPC分类号： G11C11/401 , H01L21/74 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , G11C11/40
CPC分类号： H01L21/743 , H01L21/8221 , H01L27/10841
摘要： A vertical DRAM cell using VMOS transistors and trench capacitors and the fabrication process therefor. A vertical DRAM structure comprising a VMOS transistor and trench capacitor in combination is provided wherein the access transistors are in a V-groove and the capacitors are in two vertical layers. The structure has only a single level of polysilicon and has no contacts. The memory cell circuit is a one-device memory cell, having a single access transistor with its gate connected to a word line, its drain connected to a bit line, and its source connected to a storage capacitor. More particularly, the storage capacitance node is connected to the source of the V-groove access device through a conducting bridge. The gate of the V-groove access device is connected to the polysilicon word line and the drain is a diffused region which also serves as the bit line of the cell. An epitaxial layer is grown over a combination of single crystalline material and oxide. Polycrystalline regions in the silicon substrate have an oxide covering. In an alternate version, a single crystal epitaxial layer is disposed over regions consisting of both single crystal and poly crystal Si or polycrystalline material on top of single crystalline material is converted into single crystalline material.

4. 发明授权

US4072939A Analog-to-digital and digital-to-analog converter circuits employing charge redistribution 失效
标题翻译：采用电荷再分配的模数和数模转换电路
公开(公告)号：US4072939A
公开(公告)日：1978-02-07
申请号：US662626
申请日：1976-03-01
申请人： Lawrence G. Heller , Lewis M. Terman
发明人： Lawrence G. Heller , Lewis M. Terman
IPC分类号： H03M1/44 , H01L29/768 , H01L29/78 , H03M1/00 , H03K13/03
CPC分类号： H01L29/76866 , H03M1/40 , H03M1/46 , Y10T307/352
摘要： Analog-to-digital (A/D) and digital-to-analog (D/A) converter circuits are provided using charge redistribution. The analog-to-digital converter circuit also employs successive approximation binary search techniques wherein the number of search voltages generated is a minimum. The analog-to-digital circuit includes a digital-to-analog converter circuit, a comparator circuit and a logic control means. The digital-to-analog circuit, under control of the logic means, accepts a reference voltage input and produces a sequence of search voltages which are compared with an unknown analog input voltage at the comparator. The resultant outputs from the comparator are applied to the control logic to determine the search voltage sequence. The digital-to-analog converter for the aforesaid circuit is provided in one embodiment employing charge-coupled-device technology. A substrate and two storage electrodes are combined to produce two potential storage wells and a transfer electrode is provided to move charge carriers between the storage wells. A reference charge packet Q.sub.R is stored and divided by charge redistribution between the two potential wells to produce a sequence of charge packets of value Q.sub.R /2, Q.sub.R /4, Q.sub.R /8, Q.sub.R /16 etc. which can be selectively combined to produce analog output of a D/A converter. In the A/D converter the same sequence of charge packets is used to generate the equivalent of a binary search sequence Q.sub.R /2, Q.sub.R /2.+-.Q.sub.R /4, Q.sub.R /2.+-.Q.sub.R /4.+-.Q.sub.R /8 etc. In another embodiment a bucket brigade device is provided to accomplish the same result. Because of the technique of charge redistribution wherein precise amounts of charge can be shifted in either direction between storage means, the total number of search value steps is a minimum.
摘要翻译：使用电荷再分配提供模数（A / D）和数/模（D / A）转换器电路。模数转换器电路还采用逐次逼近二进制搜索技术，其中产生的搜索电压的数量是最小的。该模数转换电路包括一个数模转换器电路，一个比较器电路和一个逻辑控制装置。在逻辑装置的控制下，数模转换电路接受参考电压输入，并产生与比较器上的未知模拟输入电压进行比较的搜索电压序列。来自比较器的结果输出被施加到控制逻辑以确定搜索电压序列。在使用电荷耦合器件技术的一个实施例中提供了用于上述电路的数模转换器。将衬底和两个存储电极组合以产生两个潜在的存储阱，并且提供转移电极以在存储阱之间移动电荷载流子。存储参考电荷分组QR，并通过两个势阱之间的电荷再分配来分割，以产生QR / 2，QR / 4，QR / 8，QR / 16等的电荷分组序列，其可以选择性地组合以产生 D / A转换器的模拟输出。在A / D转换器中，使用相同的电荷包序列来产生二进制搜索序列QR / 2，QR / 2 +/- QR / 4，QR / 2 +/- QR / 4 +/- QR / 8等。在另一实施例中，提供铲斗装置以实现相同的结果。由于电荷重新分配的技术，其中精确量的电荷可以在存储装置之间的任一方向上移动，所以搜索值步长的总数是最小的。

5. 发明授权

US5339274A Variable bitline precharge voltage sensing technique for DRAM structures 失效
标题翻译：用于DRAM结构的可变位线预充电电压感测技术
公开(公告)号：US5339274A
公开(公告)日：1994-08-16
申请号：US969644
申请日：1992-10-30
申请人： Sang H. Dhong , Toshiaki Kirihata , Hyun J. Shin , Toshio Sunaga , Yoichi Taira , Lewis M. Terman
发明人： Sang H. Dhong , Toshiaki Kirihata , Hyun J. Shin , Toshio Sunaga , Yoichi Taira , Lewis M. Terman
IPC分类号： G11C11/409 , G11C11/407 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4094
摘要： A sensing technique uses a variable precharge voltage sensing with a single bitline swing in a DRAM cell or array of DRAM cells so that the power dissipation is reduced. The bitline precharge voltage varies from one RAS cycle to the next RAS cycle depending upon the level of the data in the accessed cells. Such an arrangement eliminates the need for a reference voltage generator since the precharge voltage is not the same voltage for each RAS cycle.
摘要翻译：感测技术在DRAM单元或DRAM单元阵列中使用单个位线摆动的可变预充电电压感测，从而降低功耗。位线预充电电压根据所访问的单元中的数据的电平而从一个RAS周期到下一个RAS周期变化。这种布置消除了对参考电压发生器的需要，因为对于每个RAS周期，预充电电压不是相同的电压。

6. 发明授权

US4326192A Sequential successive approximation analog-to-digital converter 失效
标题翻译：顺序逐次逼近模数转换器
公开(公告)号：US4326192A
公开(公告)日：1982-04-20
申请号：US47557
申请日：1979-06-11
申请人： Richard B. Merrill , Lewis M. Terman , Yen S. Yee
发明人： Richard B. Merrill , Lewis M. Terman , Yen S. Yee
IPC分类号： H03M1/44 , H03M1/00 , H03M1/42 , H03K13/08
CPC分类号： H03M1/42
摘要： A pipelined analog-to-digital (A/D) conversion system enhances the effective data rate of the converter in direct proportion to the number of stages in the pipeline. The pipelined A/D converter operates in conjunction with a charge-coupled device (CCD) multilevel storage (MLS) in a three-bit (eight-level) implementation. Three comparators are used in the three-bit system arranged in a sequential successive approximation configuration with control circuits and a CCD shift register.
摘要翻译：流水线模数（A / D）转换系统与流水线中的级数成正比，提高了转换器的有效数据速率。流水线A / D转换器与三位（八电平）实现中的电荷耦合器件（CCD）多电平存储器（MLS）一起工作。在具有控制电路和CCD移位寄存器的连续逐次逼近配置中布置的三位系统中使用三个比较器。

7. 发明授权

US4306300A Multi-level charge-coupled device memory system including analog-to-digital and trigger comparator circuits 失效
标题翻译：多级电荷耦合器件存储器系统，包括模数和触发比较器电路
公开(公告)号：US4306300A
公开(公告)日：1981-12-15
申请号：US108775
申请日：1979-12-31
申请人： Lewis M. Terman , Yen S. Yee
发明人： Lewis M. Terman , Yen S. Yee
IPC分类号： G11C27/04 , G11C11/56 , G11C19/36 , H01L21/339 , H01L29/762 , G11C27/00 , G11C11/34
CPC分类号： G11C11/565 , G11C19/36 , G11C7/16
摘要： A digital-to-analog conversion (DAC) circuit and trigger comparator combination is described for encoding and decoding charge packets in a common-well multi-level signal charge-coupled memory device (CCD). The DAC circuit, which may be of the weighted capacitor type, is used to generate a staircase waveform and to create the common-well under a first gate in the CCD. The trigger comparator adjacent to a second gate in the CCD is a detection circuit which stays in one binary state until an input charge signal is received, whereupon it switches state. In particular, the weighted capacitor DAC contains an extra offset bit which is used in the analog-to-digital or regeneration operation such that when the trigger comparator switches state, the digital input to the DAC at that time correctly represents the signal charge being converted. In one embodiment a circular serial-parallel-serial memory structure is employed as the multi-level CCD memory system.
摘要翻译：描述了数模转换（DAC）电路和触发比较器组合，用于对共同井级多电平信号电荷耦合存储器件（CCD）中的电荷分组进行编码和解码。可以使用加权电容器类型的DAC电路用于产生阶梯波形并在CCD的第一栅极之下产生公共阱。与CCD中的第二栅极相邻的触发比较器是在接收到输入电荷信号之前保持一个二进制状态的检测电路，从而开关状态。特别地，加权电容DAC包含用于模数或再生操作的额外的偏移位，使得当触发比较器切换状态时，那时DAC的数字输入正确地表示被转换的信号电荷。在一个实施例中，使用圆形串行 - 并行 - 串行存储器结构作为多电平CCD存储器系统。

8. 发明授权

US5214603A Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors 失效
标题翻译：折叠的双列，超高密度动态随机存取存储器存储上述堆叠存储电容器
公开(公告)号：US5214603A
公开(公告)日：1993-05-25
申请号：US740758
申请日：1991-08-05
申请人： Sang H. Dhong , Wei Hwang , Lewis M. Terman , Matthew R. Wordeman
发明人： Sang H. Dhong , Wei Hwang , Lewis M. Terman , Matthew R. Wordeman
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10832
摘要： A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal is positioned adjacent the gate and a passing wordline is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline. In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.

9. 发明授权

US5148059A CMOS and ECL logic circuit requiring no interface circuitry 失效
标题翻译： CMOS和ECL逻辑电路不需要接口电路
公开(公告)号：US5148059A
公开(公告)日：1992-09-15
申请号：US679363
申请日：1991-04-02
申请人： Chih-Liang Chen , Peter W. Cook , Lewis M. Terman
发明人： Chih-Liang Chen , Peter W. Cook , Lewis M. Terman
IPC分类号： H03K19/0175 , H03K19/08 , H03K19/086 , H03K19/0944
CPC分类号： H03K19/09448 , H03K19/017527 , H03K19/086
摘要： An ECL circuit (12) for directly coupling to and from a CMOS circuit (10). The ECL circuit has an input node for receiving an input signal generated by a CMOS circuit. The input signal swings, or transitions, between a first potential (V.sub.0) and a second potential (V.sub.1). The ECL circuit further includes ECL core circuitry (Q.sub.3, Q.sub.4, R.sub.L), coupled to the input node and responsive the received signal, for generating an intermediate electrical signal that swings between a third potential (V.sub.2) and a fourth potential (V.sub.3) that is approximately two times (V.sub.1 -V.sub.0). The ECL circuit further includes an output driver circuit for coupling to an input of a CMOS circuit or to another ECL circuit. The output driver circuit has an input node coupled to an output of the ECL core circuitry and includes emitter followers (EF.sub.1, EF.sub.2) for generating, in response to the intermediate electrical signal swinging between V.sub.2 and V.sub.3, a first output signal tha swings between the V.sub.0 and V.sub.1.
摘要翻译：用于直接耦合到CMOS电路（10）的ECL电路（12）。 ECL电路具有用于接收由CMOS电路产生的输入信号的输入节点。输入信号在第一电位（V0）和第二电位（V1）之间摆动或转变。 ECL电路还包括耦合到输入节点并响应于接收信号的ECL核心电路（Q3，Q4，RL），用于产生在第三电位（V2）和第四电位（V3）之间摆动的中间电信号，大约是两倍（V1-V0）。 ECL电路还包括用于耦合到CMOS电路的输入或另一ECL电路的输出驱动器电路。输出驱动器电路具有耦合到ECL核心电路的输出的输入节点，并且包括发射极跟随器（EF1，EF2），用于响应于V2和V3之间的中间电信号摆动而产生第一输出信号， V0和V1。

10. 发明授权

US4137464A Charge-transfer binary search generating circuit 失效
标题翻译：电荷转移二进制搜索生成电路
公开(公告)号：US4137464A
公开(公告)日：1979-01-30
申请号：US825016
申请日：1977-08-16
申请人： Lawrence G. Heller , Lewis M. Terman
发明人： Lawrence G. Heller , Lewis M. Terman
IPC分类号： H03M1/44 , G11C11/56 , G11C19/18 , G11C19/36 , G11C27/02 , H03K4/02 , H03M1/00 , H03M1/66
CPC分类号： G11C27/024 , G11C19/186 , G11C19/36 , H03M1/804
摘要： A bucket brigade circuit is described for generating a sequence of packets of charge carriers of the form Q.sub.R /2, Q.sub.R /4, Q.sub.R /8....Q.sub.R /2.sup.N where N is an integer. The charge packets thus generated can be employed in combinations in either digital-to-analog or analog-to-digital converters. The charge generation circuit requires two equal capacitors which are used for charge redistribution. To obtain accurate quantities of charge in the generated charge packets the capacitors employed should be large, however the use of large capacitors results in low operating speed because of the large charge transfer time constants involved. The described circuit provides a scheme to reduce charge transfer time constants and therefore obtain greater speed while still permitting the use of large capacitors for high accuracy. The circuit includes a small coupling capacitor connected in series with one of the charge redistribution capacitors to produce a total capacitance which is equal to or smaller than the coupling capacitance. The sequence of charge carriers produced by the circuit can be injected into either a bucket brigade circuit or a charge-coupled-device circuit for use, for example, in digital-to-analog and analog-to-digital converters.
摘要翻译：描述了用于产生形式为QR / 2，QR / 4，QR / 8 .... QR / 2N的电荷载体的序列序列的桶旅电路，其中N是整数。这样产生的电荷包可以以数模转换器或模数转换器的组合使用。电荷产生电路需要用于电荷再分配的两个相等的电容器。为了在产生的电荷包中获得准确的电荷量，所使用的电容应该是大的，然而由于涉及大的电荷转移时间常数，使用大的电容器导致低的操作速度。所描述的电路提供了一种减少电荷转移时间常数并因此获得更高速度同时允许使用大电容器以获得高精度的方案。电路包括与电荷再分配电容器中的一个串联连接的小耦合电容器，以产生等于或小于耦合电容的总电容。由电路产生的电荷载体的序列可以被注入到例如在数模转换器和模数转换器中使用的桶式电路或电荷耦合器件电路中。

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