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1. 发明授权

US4326192A Sequential successive approximation analog-to-digital converter 失效
标题翻译：顺序逐次逼近模数转换器
公开(公告)号：US4326192A
公开(公告)日：1982-04-20
申请号：US47557
申请日：1979-06-11
申请人： Richard B. Merrill , Lewis M. Terman , Yen S. Yee
发明人： Richard B. Merrill , Lewis M. Terman , Yen S. Yee
IPC分类号： H03M1/44 , H03M1/00 , H03M1/42 , H03K13/08
CPC分类号： H03M1/42
摘要： A pipelined analog-to-digital (A/D) conversion system enhances the effective data rate of the converter in direct proportion to the number of stages in the pipeline. The pipelined A/D converter operates in conjunction with a charge-coupled device (CCD) multilevel storage (MLS) in a three-bit (eight-level) implementation. Three comparators are used in the three-bit system arranged in a sequential successive approximation configuration with control circuits and a CCD shift register.
摘要翻译：流水线模数（A / D）转换系统与流水线中的级数成正比，提高了转换器的有效数据速率。流水线A / D转换器与三位（八电平）实现中的电荷耦合器件（CCD）多电平存储器（MLS）一起工作。在具有控制电路和CCD移位寄存器的连续逐次逼近配置中布置的三位系统中使用三个比较器。

2. 发明授权

US4306300A Multi-level charge-coupled device memory system including analog-to-digital and trigger comparator circuits 失效
标题翻译：多级电荷耦合器件存储器系统，包括模数和触发比较器电路
公开(公告)号：US4306300A
公开(公告)日：1981-12-15
申请号：US108775
申请日：1979-12-31
申请人： Lewis M. Terman , Yen S. Yee
发明人： Lewis M. Terman , Yen S. Yee
IPC分类号： G11C27/04 , G11C11/56 , G11C19/36 , H01L21/339 , H01L29/762 , G11C27/00 , G11C11/34
CPC分类号： G11C11/565 , G11C19/36 , G11C7/16
摘要： A digital-to-analog conversion (DAC) circuit and trigger comparator combination is described for encoding and decoding charge packets in a common-well multi-level signal charge-coupled memory device (CCD). The DAC circuit, which may be of the weighted capacitor type, is used to generate a staircase waveform and to create the common-well under a first gate in the CCD. The trigger comparator adjacent to a second gate in the CCD is a detection circuit which stays in one binary state until an input charge signal is received, whereupon it switches state. In particular, the weighted capacitor DAC contains an extra offset bit which is used in the analog-to-digital or regeneration operation such that when the trigger comparator switches state, the digital input to the DAC at that time correctly represents the signal charge being converted. In one embodiment a circular serial-parallel-serial memory structure is employed as the multi-level CCD memory system.
摘要翻译：描述了数模转换（DAC）电路和触发比较器组合，用于对共同井级多电平信号电荷耦合存储器件（CCD）中的电荷分组进行编码和解码。可以使用加权电容器类型的DAC电路用于产生阶梯波形并在CCD的第一栅极之下产生公共阱。与CCD中的第二栅极相邻的触发比较器是在接收到输入电荷信号之前保持一个二进制状态的检测电路，从而开关状态。特别地，加权电容DAC包含用于模数或再生操作的额外的偏移位，使得当触发比较器切换状态时，那时DAC的数字输入正确地表示被转换的信号电荷。在一个实施例中，使用圆形串行 - 并行 - 串行存储器结构作为多电平CCD存储器系统。

3. 发明授权

US4130894A Loop organized serial-parallel-serial memory storage system 失效
标题翻译：循环组织串并行串行内存存储系统
公开(公告)号：US4130894A
公开(公告)日：1978-12-19
申请号：US853729
申请日：1977-11-21
申请人： Richard B. Merrill , Yen S. Yee
发明人： Richard B. Merrill , Yen S. Yee
IPC分类号： G11C7/00 , G11C19/28 , G11C19/36 , G11C27/04 , H03M1/00 , G11C27/00
CPC分类号： G11C27/04 , G11C19/287 , G11C19/36 , H03M1/1047
摘要： A functional and structural arrangement for charge-coupled device binary or multi-level storage systems of a modified serial-parallel serial type memory block arrangement wherein the output sequence is removed from the memory block proximate to the location where the original sequence was entered into the memory block. The structure includes two memory block portions designated as the left and right memory block portions. The input information sequence is entered into the upper left side of the right memory block portion in serial fashion, is moved in parallel to the bottom of the right memory block portion and serially removed from the lower left side of the right memory block portion and entered into the lower right side of the left memory block portion. The sequence is moved in parallel to the top of the left memory block portion and serially removed from the upper right side of the left memory block portion proximate to the original input location for comparison to the reference charge sequence in an analog-to-digital regeneration operation utilizing the same digital-to-analog converter.
摘要翻译：一种用于经修改的串行 - 并行串行型存储器块布置的电荷耦合器件二进制或多级存储系统的功能和结构布置，其中输出序列从接近原始序列输入到的位置的存储器块中移除内存块该结构包括被指定为左和右存储块部分的两个存储器块部分。输入信息序列以串行方式输入右存储块部分的左上侧，并行地移动到右存储块部分的底部，并从右存储块部分的左下方顺序地移除并输入进入左存储块部分的右下侧。序列与左存储块部分的顶部平行移动，并且从左存储块部分的右上方连续地从原始输入位置移除，以与模数转换中的参考电荷序列进行比较操作利用相同的数模转换器。

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