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1. 发明授权

US5418477A Data output buffer pull-down circuit for TTL interface 失效
标题翻译： TTL接口的数据输出缓冲下拉电路
公开(公告)号：US5418477A
公开(公告)日：1995-05-23
申请号：US52005
申请日：1993-04-22
申请人： Sang H. Dhong , Hyun J. Shin
发明人： Sang H. Dhong , Hyun J. Shin
IPC分类号： H03K19/017 , H03K19/0185 , H03K19/094
CPC分类号： H03K19/01721 , H03K19/018521
摘要： A pull-down circuit for a TTL compatible data output buffer uses NMOS devices. The pull-down circuit comprising two NMOS stages. Namely, a diode configuration stage where the gate and drain electrodes are shorted together during pull-down and a common-source stage. Both PMOS and NMOS devices are used for shorting the gate and drain electrodes.
摘要翻译： TTL兼容数据输出缓冲器的下拉电路使用NMOS器件。该下拉电路包括两个NMOS级。即，二极管配置阶段，其中栅极和漏极在下拉和共源级期间短路在一起。 PMOS和NMOS器件都用于短路栅极和漏极。

2. 发明授权

US5343092A Self-biased feedback-controlled active pull-down signal switching 失效
标题翻译：自偏置反馈控制有源下拉信号切换
公开(公告)号：US5343092A
公开(公告)日：1994-08-30
申请号：US874784
申请日：1992-04-27
申请人： Sang H. Dhong , Hyun J. Shin
发明人： Sang H. Dhong , Hyun J. Shin
IPC分类号： H03K19/013 , H03K19/018 , H03K19/0944 , H03K17/16 , H03K5/08
CPC分类号： H03K19/09448 , H03K19/0136
摘要： High speed, low power signal switching logic implementable in bipolar or BiCMOS technology is described. Signal switching is between a first prescribed state and a second prescribed state and is accomplished using a conventional active signal pull-up circuit in combination with a novel self-biased, feedback-controlled active signal pull-down circuit. The active signal pull-down circuit is driven by a feedback signal obtained from the active pull-up circuitry such that only a single input connection to the signal switching circuit is required. Preferably, the active signal pull-up circuit comprises an emitter follower coupled transistor and the drive signal for the active signal pull-down circuit is taken from the collector thereof via a dc-coupling level shifter. Various signal switching circuit embodiments are described.
摘要翻译：描述了在双极或BiCMOS技术中可实现的高速，低功率信号开关逻辑。信号切换处于第一规定状态和第二规定状态之间，并且使用传统的有源信号上拉电路与新型自偏置反馈控制的有源信号下拉电路相结合来完成。有源信号下拉电路由从有源上拉电路获得的反馈信号驱动，使得仅需要与信号切换电路的单个输入连接。优选地，有源信号上拉电路包括射极跟随器耦合晶体管，并且用于有源信号下拉电路的驱动信号经由直流耦合电平移位器从其集电极取出。描述各种信号切换电路实施例。

3. 发明授权

US5289432A Dual-port static random access memory cell 失效
标题翻译：双端口静态随机存取存储单元
公开(公告)号：US5289432A
公开(公告)日：1994-02-22
申请号：US690739
申请日：1991-04-24
申请人： Sang H. Dhong , Hyun J. Shin
发明人： Sang H. Dhong , Hyun J. Shin
IPC分类号： G11C11/41 , G11C8/16 , G11C11/401 , G11C8/00
CPC分类号： G11C8/16
摘要： A dual port SRAM is shown which comprises first and second word lines and first and second bit lines. A pair of semiconductor memory devices are cross coupled into a bistable circuit for storing true and complement logic levels and are coupled between common and power supply lines. A first access semiconductor is connected between the first bit line and one semiconductor memory device, and its control electrode is connected to the first word line. A second access semiconductor is connected between the second bit line and another of the semiconductor memory devices, and its control electrode is connected to the second word line. A write circuit is provided for applying write potentials to the first bit and word lines to switch the conduction states of the semiconductor memory devices. A further circuit is provided for reducing the voltage level on the power supply line when the write circuit applies the write potentials, the voltage reduction not being greater than 50% of its prereduction level, so that the potential at the second access semiconductor still exhibits a proper logic level in accordance with the memory state of the cell.
摘要翻译：示出了包括第一和第二字线以及第一和第二位线的双端口SRAM。一对半导体存储器件被交叉耦合到双稳态电路中，用于存储真实和补充逻辑电平，并且耦合在公共电源线和电源线之间。第一存取半导体连接在第一位线和一个半导体存储器件之间，其控制电极连接到第一字线。第二存取半导体连接在第二位线和另一个半导体存储器件之间，其控制电极连接到第二字线。提供写入电路用于向第一位和字线施加写入电位以切换半导体存储器件的导通状态。提供另一电路，用于在写入电路施加写入电位时降低电源线上的电压电平，电压降低不大于其预还原电平的50％，使得第二接入半导体的电位仍然呈现为正确的逻辑电平与电池的内存状态一致。

4. 发明授权

US5075566A Bipolar emitter-coupled logic multiplexer 失效
标题翻译：双极发射极耦合逻辑多路复用器
公开(公告)号：US5075566A
公开(公告)日：1991-12-24
申请号：US628252
申请日：1990-12-14
申请人： Ching-Te K. Chuang , Hyun J. Shin
发明人： Ching-Te K. Chuang , Hyun J. Shin
IPC分类号： H03K17/00 , H03K17/62 , H03K19/086
CPC分类号： H03K17/6264
摘要： A high speed multiplexer circuit is described which includes a plurality of input bipolar transistors and a reference bipolar transistor. The input and reference transistors have their emitters commonly coupled to an emitter current supply and their collectors coupled to a collector supply. The collector of the reference transistor is coupled to the collector supply through an impedance. A reference potential is connected to the base of the reference bipolar transistor and biases it for conduction. An input signal to be multiplexed is connected to the base of each of the input bipolar transistors and a diode circuit is coupled between the base of each of the input bipolar transistors and a switch input. A switch input, in a first state, causes the diode circuit to conduct and clamp the base of an input transistor, to prevent it from responding to a signal input. The switch input also manifests a second state which renders the diode circuit non-conductive and enables an input transistor to conduct in response to an input signal. The conduction of an input transistor changes current flow through the reference transistor, which change is reflected across the collector connected impedance and sensed as an output.
摘要翻译：描述了包括多个输入双极晶体管和参考双极晶体管的高速多路复用器电路。输入和参考晶体管的发射极通常耦合到发射极电流源，它们的集电极耦合到集电极电源。参考晶体管的集电极通过阻抗耦合到集电极电源。参考电位连接到参考双极晶体管的基极，并将其偏置用于导通。要复用的输入信号被连接到每个输入双极晶体管的基极，并且二极管电路耦合在每个输入双极晶体管的基极和开关输入之间。在第一状态下的开关输入使得二极管电路导通和钳位输入晶体管的基极，以防止其对信号输入进行响应。开关输入还呈现第二状态，其使得二极管电路不导通并使得输入晶体管响应于输入信号而导通。输入晶体管的导通改变通过参考晶体管的电流，该变化被反射在集电极连接的阻抗上并被感测为输出。

5. 发明授权

US5003199A Emitter coupled logic circuit having an active pull-down output stage 失效
标题翻译：发射极耦合逻辑电路具有有源下拉输出级
公开(公告)号：US5003199A
公开(公告)日：1991-03-26
申请号：US484949
申请日：1990-02-26
申请人： Ching-Te K. Chuang , Hyun J. Shin
发明人： Ching-Te K. Chuang , Hyun J. Shin
IPC分类号： H01L21/8222 , H01L21/8248 , H01L27/06 , H03K17/567 , H03K19/01 , H03K19/013 , H03K19/086
CPC分类号： H03K19/0136 , H03K17/567
摘要： An ECL circuit having an output circuit with improved pull-down characteristics. An active pull-down circuit is provided by a p-channel JFET which includes a back gate connection or a merged p-channel JFET/NPN device. The gate and/or back gate are switched, providing a lowering of the device impedance during switching of the device from pull-up to pull-down operation, resulting in an improved pull-down speed.

6. 发明授权

US5339274A Variable bitline precharge voltage sensing technique for DRAM structures 失效
标题翻译：用于DRAM结构的可变位线预充电电压感测技术
公开(公告)号：US5339274A
公开(公告)日：1994-08-16
申请号：US969644
申请日：1992-10-30
申请人： Sang H. Dhong , Toshiaki Kirihata , Hyun J. Shin , Toshio Sunaga , Yoichi Taira , Lewis M. Terman
发明人： Sang H. Dhong , Toshiaki Kirihata , Hyun J. Shin , Toshio Sunaga , Yoichi Taira , Lewis M. Terman
IPC分类号： G11C11/409 , G11C11/407 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4094
摘要： A sensing technique uses a variable precharge voltage sensing with a single bitline swing in a DRAM cell or array of DRAM cells so that the power dissipation is reduced. The bitline precharge voltage varies from one RAS cycle to the next RAS cycle depending upon the level of the data in the accessed cells. Such an arrangement eliminates the need for a reference voltage generator since the precharge voltage is not the same voltage for each RAS cycle.
摘要翻译：感测技术在DRAM单元或DRAM单元阵列中使用单个位线摆动的可变预充电电压感测，从而降低功耗。位线预充电电压根据所访问的单元中的数据的电平而从一个RAS周期到下一个RAS周期变化。这种布置消除了对参考电压发生器的需要，因为对于每个RAS周期，预充电电压不是相同的电压。

7. 发明授权

US4999518A MOS switching circuit having gate enhanced lateral bipolar transistor 失效
标题翻译： MOS开关电路具有栅极增强型横向双极晶体管
公开(公告)号：US4999518A
公开(公告)日：1991-03-12
申请号：US447984
申请日：1989-12-08
申请人： Sang H. Dhong , Chih-Liang Chen , Hyun J. Shin
发明人： Sang H. Dhong , Chih-Liang Chen , Hyun J. Shin
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/07 , H03K17/04 , H03K17/567 , H03K19/08
CPC分类号： H01L27/0711
摘要： Circuitry for implementing a gate enhanced lateral transistor to provide a circuit having a bipolar current driving capability and an FET channel voltage drop. The circuits provide switching of the lateral transistor by enabling both gate and base connections. The device is merged into an FET providing essentially no voltage drop across the collector-emitter connections permitting the collector to reach a full power supply voltage.

8. 发明授权

US5144165A CMOS off-chip driver circuits 失效
标题翻译： CMOS片外驱动电路
公开(公告)号：US5144165A
公开(公告)日：1992-09-01
申请号：US628255
申请日：1990-12-14
申请人： Sang H. Dhong , Wei Hwang , Hyun J. Shin
发明人： Sang H. Dhong , Wei Hwang , Hyun J. Shin
IPC分类号： G11C11/409 , G11C11/407 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/094
CPC分类号： H03K19/00315 , H03K19/018521 , H03K19/018571 , H03K19/09429
摘要： Output driver circuits which do not require two stacked PMOS pull-up transistors in order to interface a lower on-chip supply voltage with a higher voltage off-chip bus provide a significant savings in chip area for DRAMs. According to a first embodiment, an on-chip pump circuit generates the necessary voltage to interface to the external bus. A second embodiment detects and compares the external bus voltage to the on-chip V.sub.DD during tri-state. The higher voltage between the bus and V.sub.DD is used to control the PMOS pull-up device properly. A third embodiment is a hybrid of the first and second embodiments. The external bus is compared to V.sub.DD as in the second embodiment, but a higher-than-V.sub.DD voltage is generated on-chip as in the first embodiment. This on-chip generated voltage is used to control the PMOS pull-up device instead of the bus voltage when the bus voltage is higher than V.sub.DD.
摘要翻译：不需要两个堆叠的PMOS上拉晶体管的输出驱动器电路，以便将较低的片上电源电压与较高电压的片外总线相连，可显着节省DRAM的芯片面积。根据第一实施例，片上泵电路产生与外部总线接口所需的电压。第二实施例在三态期间检测并比较外部总线电压与片上VDD。总线和VDD之间的较高电压用于正确控制PMOS上拉器件。第三实施例是第一和第二实施例的混合。外部总线与第二实施例中的VDD相比较，但是与第一实施例中一样，片上产生高于VDD的电压。当总线电压高于VDD时，该片内产生的电压用于控制PMOS上拉器件而不是总线电压。

9. 发明授权

US5453953A Bandgap voltage reference generator 失效
标题翻译：带隙电压基准发生器
公开(公告)号：US5453953A
公开(公告)日：1995-09-26
申请号：US281236
申请日：1994-07-27
申请人： Sang H. Dhong , Hyun J. Shin , Wei Hwang
发明人： Sang H. Dhong , Hyun J. Shin , Wei Hwang
IPC分类号： G11C11/407 , G11C5/14 , G11C8/08 , H01L21/822 , H01L27/04 , G05F3/24
CPC分类号： G11C8/08 , G11C5/147
摘要： A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will track the power supply voltage and the difference between the power supply voltage and the charge reservoir voltage will be maintained substantially constant over a predefined power supply range. The voltage regulator includes a bandgap reference generator, a first differential circuit for producing a transition voltage from the reference voltage and the power supply voltage, a first transistor for comparing the power supply voltage with the boost voltage, a second transistor for comparing the transition voltage with the reference voltage and a latching comparator for equating the signal outputs from the first and second transistors so as to define a control signal for the on-chip voltage generator. Along with further specific details of the voltage regulator, a preferred bandgap reference generator is described.
摘要翻译：提供电压调节器用于控制片上电压发生器，其在电荷储存器两端产生升压电压，以供给存储器阵列中的多个字线驱动器的一个输入端。调节器被配置为使得电荷储存器电压将跟踪电源电压，并且电源电压和电荷储存器电压之间的差将在预定义的电源范围内保持基本上恒定。电压调节器包括带隙参考发生器，用于从参考电压和电源电压产生转换电压的第一差分电路，用于将电源电压与升压电压进行比较的第一晶体管，用于将转换电压与参考电压和锁存比较器，用于使来自第一和第二晶体管的信号输出相等，以便为片上电压发生器定义一个控制信号。除了电压调节器的进一步具体细节之外，还描述了优选的带隙参考发生器。

10. 发明授权

US5359552A Power supply tracking regulator for a memory array 失效
标题翻译：用于存储器阵列的电源跟踪调节器
公开(公告)号：US5359552A
公开(公告)日：1994-10-25
申请号：US163337
申请日：1993-12-06
申请人： Sang H. Dhong , Hyun J. Shin , Wei Hwang
发明人： Sang H. Dhong , Hyun J. Shin , Wei Hwang
IPC分类号： G11C11/407 , G11C5/14 , G11C8/08 , H01L21/822 , H01L27/04 , G05F1/40
CPC分类号： G11C8/08 , G11C5/147
摘要： A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will track the power supply voltage and the difference between the power supply voltage and the charge reservoir voltage will be maintained substantially constant over a predefined power supply range. The voltage regulator includes a bandgap reference generator, a first differential circuit for producing a transition voltage from the reference voltage and the power supply voltage, a first transistor for comparing the power supply voltage with the boost voltage, a second transistor for comparing the transition voltage with the reference voltage and a latching comparator for equating the signal outputs from the first and second transistors so as to define a control signal for the on-chip voltage generator. Along with further specific details of the voltage regulator, a preferred bandgap reference generator is described.
摘要翻译：提供电压调节器用于控制片上电压发生器，其在电荷储存器两端产生升压电压，以供给存储器阵列中的多个字线驱动器的一个输入端。调节器被配置为使得电荷储存器电压将跟踪电源电压，并且电源电压和电荷储存器电压之间的差将在预定义的电源范围内保持基本上恒定。电压调节器包括带隙参考发生器，用于从参考电压和电源电压产生转换电压的第一差分电路，用于将电源电压与升压电压进行比较的第一晶体管，用于将转换电压与参考电压和锁存比较器，用于使来自第一和第二晶体管的信号输出相等，以便为片上电压发生器定义一个控制信号。除了电压调节器的进一步具体细节之外，还描述了优选的带隙参考发生器。

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