专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06900092B2 Surface engineering to prevent epi growth on gate poly during selective epi processing 失效
标题翻译：表面工程，以防止在选择性epi处理期间在栅极poly上的epi生长
公开(公告)号：US06900092B2
公开(公告)日：2005-05-31
申请号：US10183336
申请日：2002-06-27
申请人： Atul C. Ajmera , Dominic J. Schepis , Michael D. Steigerwalt
发明人： Atul C. Ajmera , Dominic J. Schepis , Michael D. Steigerwalt
IPC分类号： H01L21/20 , H01L21/336 , H01L29/78 , H01L21/8238 , H01L21/31 , H01L21/3205
CPC分类号： H01L29/7834 , H01L21/02532 , H01L21/02639 , H01L29/66628 , Y10S438/976
摘要： The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.
摘要翻译：本发明提供一种在多晶硅栅电极顶上形成氮化表面层的方法，该多晶硅栅电极抑制其上的外延硅层的生长。具体地说，本发明的方法包括以下步骤：在栅极电介质层的顶部形成多晶硅层，在多晶硅层上形成氮化表面层; 选择性地去除氮化表面层和多晶硅层的部分，停留在栅极介电层上，同时在栅极电介质层上留下图案化的氮化表面层和多晶硅层的叠层; 在多晶硅层的至少暴露的垂直侧壁上形成侧壁间隔物; 去除不被侧壁间隔物保护的栅极电介质层的部分; 以及在下面的半导体衬底的暴露的水平表面上生长外延硅层。

2. 发明授权

US06440807B1 Surface engineering to prevent EPI growth on gate poly during selective EPI processing 有权
标题翻译：表面工程，以防止EPI在选择性EPI加工过程中对聚酰胺的生长
公开(公告)号：US06440807B1
公开(公告)日：2002-08-27
申请号：US09882095
申请日：2001-06-15
申请人： Atul C. Ajmera , Dominic J. Schepis , Michael D. Steigerwalt
发明人： Atul C. Ajmera , Dominic J. Schepis , Michael D. Steigerwalt
IPC分类号： H01L21336
CPC分类号： H01L29/7834 , H01L21/02532 , H01L21/02639 , H01L29/66628 , Y10S438/976
摘要： The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.
摘要翻译：本发明提供一种在多晶硅栅电极顶上形成氮化表面层的方法，该多晶硅栅电极抑制其上的外延硅层的生长。具体地说，本发明的方法包括以下步骤：在栅极电介质层的顶部形成多晶硅层，在多晶硅层上形成氮化表面层; 选择性地去除氮化表面层和多晶硅层的部分，停留在栅极介电层上，同时在栅极电介质层上留下图案化的氮化表面层和多晶硅层的叠层; 在多晶硅层的至少暴露的垂直侧壁上形成侧壁间隔物; 去除不被侧壁间隔物保护的栅极电介质层的部分; 以及在下面的半导体衬底的暴露的水平表面上生长外延硅层。

3. 发明授权

US06437377B1 Low dielectric constant sidewall spacer using notch gate process 失效
标题翻译：低介电常数侧壁间隔板采用切口浇口工艺
公开(公告)号：US06437377B1
公开(公告)日：2002-08-20
申请号：US09768525
申请日：2001-01-24
申请人： Atul C. Ajmera , Ka Hing (Samuel) Fung , Victor Ku , Dominic J. Schepis
发明人： Atul C. Ajmera , Ka Hing (Samuel) Fung , Victor Ku , Dominic J. Schepis
IPC分类号： H01L2710
CPC分类号： H01L29/4991 , H01L21/28114 , H01L21/28194 , H01L29/42364 , H01L29/4983 , H01L29/51 , H01L29/6656 , H01L29/6659
摘要： A notched gate MOS device includes either an encapsulated low dielectric material or encapsulated air or a vacuum at the bottom of a notched gate. Due to the low dielectric constant at the site of interface between the gate and the source/drain, the capacitance loss at that site is significantly reduced.
摘要翻译：缺口门MOS器件包括封装的低介电材料或封装的空气或在缺口栅极的底部的真空。由于栅极和源极/漏极之间的界面位置处的介电常数低，所以该位置处的电容损耗显着降低。

4. 发明授权

US06602759B2 Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon 有权
公开(公告)号：US06602759B2
公开(公告)日：2003-08-05
申请号：US09731620
申请日：2000-12-07
申请人： Atul C. Ajmera , Klaus D. Beyer , Dominic J. Schepis
发明人： Atul C. Ajmera , Klaus D. Beyer , Dominic J. Schepis
IPC分类号： H01L2176
CPC分类号： H01L21/76227
摘要： A method for forming an isolation trench in a silicon or silicon-on-insulator substrate is described in which a trench is formed in the semiconductor structure (containing a multiple layer structure of Si, SiO2, and SiN layers) and an undoped polysilicon layer is deposited on the bottom and sidewalls of the trench and on the surface of the region adjacent to the trench. A substantial portion of the trench is left unfilled by the undoped polysilicon layer deposited. The polysilicon layer is thermally oxidized to form a thermal oxide that fills the trench and thereby avoids forming a birds-beak formation of the thermal oxide above the sidewalls of the trench. The isolation structure may be planarized by either removing the polysilicon layer from the region adjacent to the trench before oxidation or later removing the oxide from the SiN layer and adjusting height of the oxide in the trench. Alternatively, either a doped polysilicon layer or a doped SiO2 layer may be formed above the silicon nitride layer before the undoped polysilicon layer is deposited. In this case, the isolation structure is heat treated prior to oxidization to drive dopants from the doped layer into the undoped polysilicon layer, thereby forming a secondarily doped polysilicon layer from the undoped polysilicon layer. The doped layers are then removed by selective wet etching and expose the silicon nitride layer prior to oxidation.

5. 发明授权

US06506649B2 Method for forming notch gate having self-aligned raised source/drain structure 有权
标题翻译：用于形成具有自对准凸起源极/漏极结构的陷波栅的方法
公开(公告)号：US06506649B2
公开(公告)日：2003-01-14
申请号：US09811706
申请日：2001-03-19
申请人： Ka Hing Fung , Atul C. Ajmera , Victor Ku , Dominic J. Schepis
发明人： Ka Hing Fung , Atul C. Ajmera , Victor Ku , Dominic J. Schepis
IPC分类号： H01L21336
CPC分类号： H01L29/66628 , H01L29/42376 , H01L29/665 , H01L29/7835
摘要： An innovative MOSFET having a raised source drain (RSD) is constructed prior to implanting source-drain dopants. The RSD structure thus built has a distinct advantage in that the offset from the RSD to the MOSFET channel is fully adjustable to minimize the overlap capacitance in the device. The RSD construction uses a selective epitaxial process to effectively reduce the drain-source resistance. This improvement is even more significant in thin-film SOI technology. Using an RSD, the film outside the channel area thickens which, in turn, reduces the parasitic resistance. The method of constructing such a structure includes the steps of: forming a notch gate on a top surface of a substrate; covering the notch gate and the top surface of the substrate with a conformal dielectric film; etching the dielectric film to expose an upper surface of the notch gate and selected exposed areas of the substrate; selectively growing silicon on the etched surface of the gate notch and on the etched surface of the substrate; implanting doping to form a drain-source area; forming spacers on the vertical walls of the notch gate; and forming a salicide on the notch gate and on the source and drain areas. The MOSFET device may be alternately be built without the formation of spacers.
摘要翻译：在植入源极 - 漏极掺杂剂之前，构建了具有升高的源极漏极（RSD）的创新型MOSFET。如此构建的RSD结构具有明显的优点，即从RSD到MOSFET通道的偏移是完全可调的，以最小化器件中的重叠电容。 RSD结构使用选择性外延工艺来有效降低漏极 - 源极电阻。这种改进在薄膜SOI技术中更为显着。使用RSD，通道区域外部的膜变厚，这又降低了寄生电阻。构造这种结构的方法包括以下步骤：在衬底的顶表面上形成陷波门; 用保形绝缘膜覆盖基板的切口栅和顶表面; 蚀刻电介质膜以暴露陷波栅的上表面和基板的选定的曝光区域; 选择性地在栅极刻蚀的蚀刻表面上和衬底的蚀刻表面上生长硅; 注入掺杂以形成漏 - 源区; 在凹口门的垂直壁上形成间隔物; 并在凹口门和源极和漏极区域上形成自对准硅化物。可以交替地构建MOSFET器件而不形成间隔物。

6. 发明授权

US07091128B2 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs 失效
标题翻译：避免氧化物底切在薄间隔FET预硅化物清洗过程中的方法
公开(公告)号：US07091128B2
公开(公告)日：2006-08-15
申请号：US11266855
申请日：2005-11-04
申请人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A. Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
发明人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A. Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L21/302
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.
摘要翻译：描述了在预硅化物清洁步骤期间以避免电介质层底切的方式形成CMOS器件的方法。在形成包括半导体衬底表面上的栅极堆叠的CMOS器件的情况下，图案化栅极堆叠包括在具有垂直侧壁的导体下方的栅极电介质，在衬底表面之上和之上形成介电层。在每个垂直侧壁处形成覆盖在电介质层上的各种氮化物间隔元件。使用蚀刻工艺去除衬底表面上的电介质层，使得保留每个间隔物下面的介电层的一部分。然后，在整个样品（栅极堆叠，每个栅极侧壁和衬底表面处的间隔元件）上沉积氮化物层，然后通过蚀刻工艺去除，使得仅一部分所述氮化物膜（“插塞”）遗迹。插头密封并封装每个所述间隔件下面的电介质层，从而防止在随后的硅化物前处理过程中电介质材料被切削。通过防止底切，本发明还防止蚀刻停止膜（在接触形成之前沉积）与栅极氧化物接触。因此，能够实现提高晶体管驱动电流所需的薄间隔晶体管几何形状的集成。

7. 发明授权

US06566210B2 Method of improving gate activation by employing atomic oxygen enhanced oxidation 失效
标题翻译：通过采用原子氧增强氧化改善浇口活化的方法
公开(公告)号：US06566210B2
公开(公告)日：2003-05-20
申请号：US09905233
申请日：2001-07-13
申请人： Atul C. Ajmera , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
发明人： Atul C. Ajmera , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
IPC分类号： H01L21336
CPC分类号： H01L21/28035 , H01L21/32105 , H01L29/4916
摘要： The present invention provides a method of preparing a Si-based metal-insulator-semiconductor (MIS) transistor which prevents the polycrystalline grains of the gate conductor from getting significantly larger by reducing the thermal budget of the sidewall oxidation process. The thermal budget of the inventive sidewall oxidation process is reduced one or two orders of magnitude over conventional prior art sidewall oxidation processes by utilizing atomic oxygen as the oxidizing ambient. The present invention also provides Si-based MIS transistors having a gate conductor having grain sizes of about 0.1, preferably 0.05, &mgr;m or less.
摘要翻译：本发明提供一种制备Si基金属 - 绝缘体半导体（MIS）晶体管的方法，其通过降低侧壁氧化工艺的热量预算来防止栅极导体的多晶晶粒变得明显更大。通过利用原子氧作为氧化环境，本发明的侧壁氧化过程的热预算比常规现有技术的侧壁氧化过程减少一到两个数量级。本发明还提供具有晶体尺寸为约0.1μm，优选0.05μm或更小的栅极导体的Si基MIS晶体管。

8. 发明授权

US06605521B2 Method of forming an oxide film on a gate side wall of a gate structure 有权
公开(公告)号：US06605521B2
公开(公告)日：2003-08-12
申请号：US10265729
申请日：2002-10-08
申请人： Atul C. Ajmera , Karanam Balasubramanyam , Tomio Katata , Shang-Bin Ko
发明人： Atul C. Ajmera , Karanam Balasubramanyam , Tomio Katata , Shang-Bin Ko
IPC分类号： H01L214763
CPC分类号： H01L21/32105 , H01L21/28061 , H01L29/4933
摘要： In order to prevent abnormal oxidation of the side wall of a polycide gate conductor layer in the oxidation heat treatment process after the RIE processing of the polycide gate conductor layer in a semiconductor memory cell, the heat treatment for oxidizing the side wall of the polycide gate conductor layer is conducted in two steps with different conditions. By conducting the first heat treatment process in an inert atmosphere, a thin oxide film is formed on the side wall of the polycide tungsten/gate conductor layer. Then by conducting the second heat treatment process in an atmosphere with a strong oxidizing property, a thick oxide film without abnormal oxidation can be formed.

9. 发明授权

US06566198B2 CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture 失效
标题翻译：具有非外延凸起源极/漏极和自对准栅极的CMOS结构及其制造方法
公开(公告)号：US06566198B2
公开(公告)日：2003-05-20
申请号：US09821520
申请日：2001-03-29
申请人： Heemyong Park , Fariborz Assaderaghi , Atul C. Ajmera , Ghavam G. Shahidi
发明人： Heemyong Park , Fariborz Assaderaghi , Atul C. Ajmera , Ghavam G. Shahidi
IPC分类号： H01L21336
CPC分类号： H01L29/78696 , H01L21/823814 , H01L27/092 , H01L29/41733 , H01L29/458 , H01L29/66553 , H01L29/66583 , H01L29/66772 , H01L29/78684
摘要： A CMOS structure and method of achieving self-aligned raised source/drain for CMOS structures on SOI without relying on selective epitaxial growth of silicon. In the method, CMOS structures are provided by performing sacrificial oxidation so that oxidation occurs on the surface of both the SOI and BOX interface. This allows for oxide spacer formation for gate-to-source/drain isolation which makes possible raised source/drain fabrication without increasing contact resistance.
摘要翻译：在SOI上实现CMOS结构的自对准凸起源极/漏极的CMOS结构和方法，而不依赖于硅的选择性外延生长。在该方法中，通过进行牺牲氧化来提供CMOS结构，使得在SOI和BOX界面的表面上发生氧化。这允许用于栅极至源极/漏极隔离的氧化物间隔物形成，这使得可能的升高的源极/漏极制造而不增加接触电阻。

10. 发明授权

US08461009B2 Spacer and process to enhance the strain in the channel with stress liner 失效
标题翻译：间距和过程，以增强通道中应力衬里的应变
公开(公告)号：US08461009B2
公开(公告)日：2013-06-11
申请号：US11307928
申请日：2006-02-28
申请人： Atul C. Ajmera , Christopher V. Baiocco , Xiangdong Chen , Wenzhi Gao , Young Way Teh
发明人： Atul C. Ajmera , Christopher V. Baiocco , Xiangdong Chen , Wenzhi Gao , Young Way Teh
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.
摘要翻译：通过应力衬垫，间隔物，集成电路形成工艺和集成电路增强通道中的应变的方法。将由第一氧化物和第一氮化物层构成的第一间隔物施加到基板上的栅电极，并施加由第二氧化物和第二氮化物层构成的第二间隔物。在衬底中深入植入源极和漏极，并且去除第二氮化物，第二氧化物和第一氮化物层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式