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1. 发明申请

US20050167742A1 Power semiconductor devices and methods of manufacture 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20050167742A1
公开(公告)日：2005-08-04
申请号：US11026276
申请日：2004-12-29
申请人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
IPC分类号： G06F1/26 , H01L21/265 , H01L21/3065 , H01L21/311 , H01L21/336 , H01L21/68 , H01L23/495 , H01L23/498 , H01L29/06 , H01L29/165 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H02M3/00 , H02M3/335
CPC分类号： H01L29/7802 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66734 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2224/16245 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.
摘要翻译：公开了用于改进的功率器件的各种实施例及其制造方法，封装和结合其的用于各种功率电子应用的电路。本发明的一个方面结合了许多电荷平衡技术和用于减小寄生电容的其它技术，以获得具有改进的电压性能，较高开关速度和较低导通电阻的功率器件的不同实施例。本发明的另一方面提供了用于低，中和高电压装置的改进的端接结构。根据本发明的其它方面提供了改进的功率器件制造方法。提出了具体的处理步骤的改进，例如沟槽的形成，沟槽内的电介质层的形成，台面结构的形成以及用于降低衬底厚度的工艺等。根据本发明的另一方面，电荷平衡功率器件在同一管芯上并入温度和电流检测元件，例如二极管。本发明的其它方面改进了用于功率器件的等效串联电阻（ESR），在与功率器件相同的芯片上并入附加电路，并提供对电荷平衡功率器件的封装的改进。

2. 发明申请

US20070155104A1 Power device utilizing chemical mechanical planarization 失效
标题翻译：利用化学机械平面化的功率器件
公开(公告)号：US20070155104A1
公开(公告)日：2007-07-05
申请号：US11327657
申请日：2006-01-05
申请人： Bruce Marchant , Thomas Grebs , Rodney Ridley , Nathan Kraft
发明人： Bruce Marchant , Thomas Grebs , Rodney Ridley , Nathan Kraft
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/7811 , H01L21/3083 , H01L29/0696 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/7813 , Y10S438/942 , Y10S438/95
摘要： A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.
摘要翻译：沟槽门控场效应晶体管（FET）如下形成。使用一个掩模，多个有源栅极沟槽和至少一个栅极流道沟槽被限定并同时形成在硅区域中，使得（i）至少一个栅极流道沟槽的宽度大于多个栅极沟槽的宽度的有源栅极沟槽，以及（ii）多个有源栅极沟槽与至少一个栅极流道沟槽邻接。

3. 发明申请

US20060273386A1 Trench-gate field effect transistors and methods of forming the same 失效
标题翻译：沟槽栅场效应晶体管及其形成方法
公开(公告)号：US20060273386A1
公开(公告)日：2006-12-07
申请号：US11441386
申请日：2006-05-24
申请人： Hamza Yilmaz , Daniel Calafut , Christopher Kocon , Steven Sapp , Dean Probst , Nathan Kraft , Thomas Grebs , Rodney Ridley , Gary Dolny , Bruce Marchant , Joseph Yedinak
发明人： Hamza Yilmaz , Daniel Calafut , Christopher Kocon , Steven Sapp , Dean Probst , Nathan Kraft , Thomas Grebs , Rodney Ridley , Gary Dolny , Bruce Marchant , Joseph Yedinak
IPC分类号： H01L29/94
CPC分类号： H01L29/7827 , H01L21/26586 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/872
摘要： A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.
摘要翻译：场效应晶体管包括在第二导电类型的半导体区域上的第一导电类型的体区。栅极沟槽延伸穿过身体区域并终止在半导体区域内。至少一个导电屏蔽电极设置在栅极沟槽中。栅极电极设置在栅极沟槽中，但与至少一个导电屏蔽电极绝缘。屏蔽介电层绝缘至少一个导电屏蔽电极与半导体区域。栅极电介质层使栅电极与体区绝缘。屏蔽电介质层形成为使其伸出并直接延伸到身体区域下方。

4. 发明申请

US20060214221A1 Power semiconductor devices and methods of manufacture 有权
公开(公告)号：US20060214221A1
公开(公告)日：2006-09-28
申请号：US11445020
申请日：2006-05-31
申请人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
IPC分类号： H01L29/76
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

5. 发明申请

US20060214222A1 Power semiconductor devices and methods of manufacture 有权
公开(公告)号：US20060214222A1
公开(公告)日：2006-09-28
申请号：US11445111
申请日：2006-05-31
申请人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J. Lee , Peter Wilson , Joseph Yedinak , J. Jung , H. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J. Lee , Peter Wilson , Joseph Yedinak , J. Jung , H. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
IPC分类号： H01L29/76
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

6. 发明授权

US07078296B2 Self-aligned trench MOSFETs and methods for making the same 有权
标题翻译：自对准沟槽MOSFET及其制造方法
公开(公告)号：US07078296B2
公开(公告)日：2006-07-18
申请号：US10052234
申请日：2002-01-16
申请人： Duc Chau , Becky Losee , Bruce Marchant , Dean Probst , Robert Herrick , James Murphy
发明人： Duc Chau , Becky Losee , Bruce Marchant , Dean Probst , Robert Herrick , James Murphy
IPC分类号： H01L21/8232
CPC分类号： H01L27/088 , H01L21/823487
摘要： Self-aligned trench MOSFETs and methods for manufacturing the same are disclosed. By having a self-aligned structure, the number of MOSFETS per unit area—the cell density—is increased, making the MOSFETs cheaper to produce. The self-aligned structure for the MOSFET is provided by making the sidewall of the overlying isolation dielectric layer substantially aligned with the sidewall of the gate conductor. Such an alignment can be made through any number of methods such as using a dual dielectric process, using a selective dielectric oxidation process, using a selective dielectric deposition process, or a spin-on-glass dielectric process.
摘要翻译：公开了自对准沟槽MOSFET及其制造方法。通过具有自对准结构，每单位面积的MOSFET的数量（单元密度）增加，使得MOSFET更便宜地生产。 MOSFET的自对准结构通过使覆盖隔离电介质层的侧壁基本上与栅极导体的侧壁对准来提供。这种对准可以通过任何数量的方法进行，例如使用双电介质方法，使用选择性介电氧化工艺，使用选择性电介质沉积工艺或旋涂玻璃介电工艺。

7. 发明申请

US20050029618A1 Structure and method of forming a dual-trench field effect transistor 审中-公开
标题翻译：形成双沟道场效应晶体管的结构和方法
公开(公告)号：US20050029618A1
公开(公告)日：2005-02-10
申请号：US10934969
申请日：2004-09-03
申请人： Bruce Marchant
发明人： Bruce Marchant
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/1095
摘要： A field effect transistor includes a semiconductor region of a first conductivity type and a well region of a second conductivity type over the semiconductor region. A source region of the first conductivity type is in an upper portion of the well region. A gate trench is adjacent to the source region. The gate trench extends through the well region and terminates within an upper half of the semiconductor region. A stripe trench extends through the well region and terminates within a lower half of the semiconductor region. The stripe trench is filled with a semiconductor material of the second conductivity type such that: (i) the filled stripe trench is contiguous with the well region, and (ii) the semiconductor material of the second conductivity type forms a PN junction with the semiconductor region.
摘要翻译：场效应晶体管包括在半导体区域上的第一导电类型的半导体区域和第二导电类型的阱区域。第一导电类型的源极区位于阱区的上部。栅极沟槽与源极区域相邻。栅极沟槽延伸穿过阱区并终止在半导体区域的上半部分内。条纹沟槽延伸穿过阱区并终止在半导体区域的下半部分内。条状沟槽填充有第二导电类型的半导体材料，使得：（i）填充条纹沟槽与阱区域邻接，并且（ii）第二导电类型的半导体材料与半导体形成PN结地区。

8. 发明申请

US20070221952A1 High density trench FET with integrated Schottky diode and method of manufacture 有权
标题翻译：具有集成肖特基二极管的高密度沟槽FET及其制造方法
公开(公告)号：US20070221952A1
公开(公告)日：2007-09-27
申请号：US11388790
申请日：2006-03-24
申请人： Paul Thorup , Ashok Challa , Bruce Marchant
发明人： Paul Thorup , Ashok Challa , Bruce Marchant
IPC分类号： H01L29/74
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/407 , H01L29/66727 , H01L29/66734 , H01L29/7806
摘要： A monolithically integrated trench FET and Schottky diode includes a pair of trenches terminating in a first silicon region of first conductivity type. Two body regions of a second conductivity type separated by a second silicon region of the first conductivity type are located between the pair of trenches. A source region of the first conductivity type is located over each body region. A contact opening extends between the pair of trenches to a depth below the source regions. An interconnect layer fills the contact opening so as to electrically contact the source regions and the second silicon region. Where the interconnect layer electrically contacts the second silicon region, a Schottky contact is formed.
摘要翻译：单片集成沟槽FET和肖特基二极管包括终止于第一导电类型的第一硅区的一对沟槽。由第一导电类型的第二硅区隔开的第二导电类型的两个主体区域位于该对沟槽之间。第一导电类型的源极区域位于每个主体区域上。接触开口在该对沟槽之间延伸到源区域下方的深度。互连层填充接触开口以便电接触源区和第二硅区。当互连层与第二硅区电接触时，形成肖特基接触。

9. 发明授权

US08536042B2 Method of forming a topside contact to a backside terminal of a semiconductor device 有权
标题翻译：在半导体器件的背面端子上形成顶部接触的方法
公开(公告)号：US08536042B2
公开(公告)日：2013-09-17
申请号：US12982509
申请日：2010-12-30
申请人： John T. Andrews , Hamza Yilmaz , Bruce Marchant , Ihsiu Ho
发明人： John T. Andrews , Hamza Yilmaz , Bruce Marchant , Ihsiu Ho
IPC分类号： H01L21/44
CPC分类号： H01L29/7811 , H01L24/12 , H01L29/0657 , H01L29/41741 , H01L29/41766 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7809 , H01L29/7813 , H01L29/872 , H01L2924/01055 , H01L2924/12032 , H01L2924/13055 , H01L2924/13091 , H01L2924/3025 , H01L2924/00
摘要： A process for forming a vertically conducting semiconductor device includes providing a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. The process also includes forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. The method also includes forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.
摘要翻译：形成垂直导电半导体器件的工艺包括提供具有顶侧表面和背面的半导体衬底。半导体衬底用作垂直传导器件的端子，用于在操作期间偏压垂直传导器件。该工艺还包括形成在半导体衬底的顶侧表面上延伸但在到达半导体衬底的边缘之前终止的外延层，以沿着半导体衬底的周边形成凹陷区域。该方法还包括形成延伸到凹陷区域中但在到达半导体衬底的边缘之前终止的互连层。互连层在凹陷区域中电接触半导体衬底的顶侧表面，从而提供与半导体衬底的顶侧接触。

10. 发明授权

US07884390B2 Structure and method of forming a topside contact to a backside terminal of a semiconductor device 有权
标题翻译：在半导体器件的背面端子上形成顶部接触的结构和方法
公开(公告)号：US07884390B2
公开(公告)日：2011-02-08
申请号：US12168348
申请日：2008-07-07
申请人： John T. Andrews , Hamza Yilmaz , Bruce Marchant , Ihsiu Ho
发明人： John T. Andrews , Hamza Yilmaz , Bruce Marchant , Ihsiu Ho
IPC分类号： H01L29/732
CPC分类号： H01L29/7811 , H01L24/12 , H01L29/0657 , H01L29/41741 , H01L29/41766 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7809 , H01L29/7813 , H01L29/872 , H01L2924/01055 , H01L2924/12032 , H01L2924/13055 , H01L2924/13091 , H01L2924/3025 , H01L2924/00
摘要： A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but terminates prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. An interconnect layer extends into the recessed region but terminates prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.
摘要翻译：垂直导电半导体器件包括具有顶侧表面和背面的半导体衬底。半导体衬底用作垂直传导器件的端子，用于在操作期间偏压垂直传导器件。外延层在半导体衬底的顶侧表面上延伸，但在到达半导体衬底的边缘之前终止，以沿着半导体衬底的周边形成凹陷区域。互连层延伸到凹陷区域中，但在到达半导体衬底的边缘之前终止。互连层在凹陷区域中电接触半导体衬底的顶侧表面，从而提供与半导体衬底的顶侧接触。

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