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1. 发明授权

US08732635B2 Apparatus and methods for power management in integrated circuits 有权
标题翻译：集成电路中电源管理的装置和方法
公开(公告)号：US08732635B2
公开(公告)日：2014-05-20
申请号：US12165665
申请日：2008-07-01
申请人： David Lewis , Christopher F. Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
发明人： David Lewis , Christopher F. Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
IPC分类号： G06F17/50 , G06F9/455 , H03K3/01 , G05F1/10
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
摘要翻译：可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。控制电路耦合到非易失性存储器和配置存储器。一组电压从控制电路的输出导出，并被应用于PLD内的电路。

2. 发明授权

US07589552B1 Integrated circuit with redundancy 有权
标题翻译：集成电路冗余
公开(公告)号：US07589552B1
公开(公告)日：2009-09-15
申请号：US11977293
申请日：2007-10-23
申请人： Mario E. Guzman , Christopher F. Lane
发明人： Mario E. Guzman , Christopher F. Lane
IPC分类号： H03K19/003
CPC分类号： H03K19/0075
摘要： Integrated circuits such as programmable logic devices are provided that have circuit blocks such as memory blocks. The integrated circuits may be tested to determine whether the circuit blocks contain defects. If defective circuitry is identified, switching circuitry in the circuit blocks can be configured to switch redundant circuitry into use. Repairs may be made by loading repair data into fuses on the integrated circuit. Each circuit block may have an associated control circuit with a unique address. A master block repair controller may be used to route repair data to each control circuit over a shared bus using the unique addresses of the control circuits. Each control circuit may have register circuitry into which addresses and repair data are loaded. Testing circuitry may be used to supply test signals. Multiplexing circuitry can selectively route either the test signals or repair data to the control circuits over the shared bus.
摘要翻译：提供诸如可编程逻辑器件的集成电路，其具有诸如存储器块的电路块。可以测试集成电路以确定电路块是否包含缺陷。如果识别出有故障的电路，电路块中的开关电路可以配置为将冗余电路切换到使用状态。可以通过将修理数据加载到集成电路上的熔丝中进行维修。每个电路块可以具有具有唯一地址的相关控制电路。主块修复控制器可用于使用控制电路的唯一地址通过共享总线将修复数据路由到每个控制电路。每个控制电路可以具有寄存器电路，地址和修复数据被加载到寄存器电路中。测试电路可用于提供测试信号。复用电路可以通过共享总线选择性地将测试信号或维修数据路由到控制电路。

3. 发明申请

US20080253220A1 Flexible RAM Clock Enable 有权
标题翻译：灵活的RAM时钟使能
公开(公告)号：US20080253220A1
公开(公告)日：2008-10-16
申请号：US12145440
申请日：2008-06-24
申请人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
发明人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
IPC分类号： G11C8/18
CPC分类号： G11C7/1075 , G11C8/18 , H03K19/1737
摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.
摘要翻译：第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。

4. 发明授权

US07432734B2 Versatile logic element and logic array block 有权
公开(公告)号：US07432734B2
公开(公告)日：2008-10-07
申请号：US11743625
申请日：2007-05-02
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

5. 发明授权

US07295036B1 Method and system for reducing static leakage current in programmable logic devices 有权
标题翻译：用于减少可编程逻辑器件中的静态漏电流的方法和系统
公开(公告)号：US07295036B1
公开(公告)日：2007-11-13
申请号：US11291712
申请日：2005-11-30
申请人： Ketan H. Zaveri , Christopher F. Lane
发明人： Ketan H. Zaveri , Christopher F. Lane
IPC分类号： H03K19/173
CPC分类号： H03K19/17772 , H03K19/17728 , H03K19/17784
摘要： A programmable logic device having logic block that can be selectively placed in a reduced power consumption mode is provided. The PLD includes a plurality of logic array blocks (LABs) and a plurality of interconnects defining signal pathways between the plurality of LABs. Sleep control logic of the PLD issues a sleep control signal for placing at least a portion of the plurality of LABs in a sleep mode. Bias control logic of the PLD is in communication with the sleep control logic. The bias control logic is triggered by the sleep control signal to issue a first bias control signal and a second bias control signal. The first and second bias control signals are transmitted to corresponding transistors of the LABS. The first and second bias control signals apply a reverse bias to corresponding transistor wells to increase threshold voltages for the respective transistors.
摘要翻译：提供了具有逻辑块的可编程逻辑器件，其可以选择性地放置在降低的功耗模式中。 PLD包括多个逻辑阵列块（LAB）和定义多个LAB之间的信号路径的多个互连。 PLD的休眠控制逻辑发出睡眠控制信号，用于将多个LAB的至少一部分放置在睡眠模式中。 PLD的偏置控制逻辑与睡眠控制逻辑通信。偏置控制逻辑由休眠控制信号触发，以发出第一偏置控制信号和第二偏置控制信号。第一和第二偏置控制信号被传送到LABS的相应晶体管。第一和第二偏置控制信号向对应的晶体管阱施加反向偏置以增加相应晶体管的阈值电压。

6. 发明授权

US06970014B1 Routing architecture for a programmable logic device 失效
标题翻译：可编程逻辑器件的路由架构
公开(公告)号：US06970014B1
公开(公告)日：2005-11-29
申请号：US10623709
申请日：2003-07-21
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Brian D. Johnson , Richard Cliff , Srinivas T. Reddy , Christopher F. Lane , Cameron R. McClintock , Vaughn Betz , Chris Wysocki , Alexander R. Marquardt
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Brian D. Johnson , Richard Cliff , Srinivas T. Reddy , Christopher F. Lane , Cameron R. McClintock , Vaughn Betz , Chris Wysocki , Alexander R. Marquardt
IPC分类号： H03K19/177
CPC分类号： H03K19/17736
摘要： An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides.
摘要翻译：本发明的实施例涉及在可编程逻辑器件（“PLD”）内互连诸如逻辑阵列块（“LAB”）的功能块的3边路由架构。在三面路由架构中，功能块第一侧的输入和输出连接到第一通道，功能块第二侧上的输入和输出连接到第二通道，其中第二侧与第一通道相反侧。功能块第三侧的输入和输出连接到第三个通道。与功能块的第四侧相关联的与第三侧相反的第四侧的第四通道仅耦合到第一通道和第二通道。在一种配置中，第一侧，第二侧和第三侧中的每一个上的输入和输出具有相等数量的输入和输出。在该配置中，第一通道，第二通道和第三通道中的每一个具有相同的宽度。在另一种构造中，第一侧，第二侧或第三侧中的一个上的引脚数目与另一侧上的引脚数不同。

7. 发明授权

US06819135B2 Fast signal conductor networks for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的快速信号导线网络
公开(公告)号：US06819135B2
公开(公告)日：2004-11-16
申请号：US10047468
申请日：2002-01-14
申请人： Christopher F. Lane , Srinivas T. Reddy
发明人： Christopher F. Lane , Srinivas T. Reddy
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas. A so-called “fast conductor” network is provided on the device for rapidly and efficiently distributing a relatively small number of signals to substantially any logic area on the device. The fast conductor network has several main conductors that substantially bisect the array in one direction (e.g., by extending parallel to the column axis). Some main conductors can carry signals from off the device. Other main conductors can carry signals generated on the device. The network further includes secondary conductors that extend transverse to the main conductors (e.g., along each row of logic areas). Programmable logic connectors are provided for selectively applying signals from the main conductors to the secondary conductors and from the secondary conductors to the logic areas.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该可编程逻辑区域以这种区域的交叉行和列的二维阵列布置在器件上。在设备上提供了所谓的“快速导体”网络，用于将相对较少数量的信号快速有效地分配到设备上的基本上任何逻辑区域。快速导体网络具有几个主导体，其在一个方向上基本上平分阵列（例如，通过平行于列轴线延伸）。一些主导体可以携带离开设备的信号。其他主导体可以携带在设备上产生的信号。网络还包括横向于主导体（例如，沿着每一排逻辑区域）延伸的次级导体。提供可编程逻辑连接器，用于选择性地将信号从主导体施加到次级导体，并从次导体到逻辑区域。

8. 发明授权

US06798242B2 Programmable logic device with hierarchical interconnection resources 失效
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06798242B2
公开(公告)日：2004-09-28
申请号：US10426991
申请日：2003-04-29
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。本地导体与每个区域相关联，主要用于使信号进入该区域。在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

9. 发明授权

US06577160B2 Programmable logic device with hierarchical interconnection resources 有权
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06577160B2
公开(公告)日：2003-06-10
申请号：US10170026
申请日：2002-06-10
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region. Local conductors are associated with each region. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联。本地导体与每个区域相关联。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

10. 发明授权

US06356110B1 Multifunction memory array in a programmable logic device 有权
标题翻译：可编程逻辑器件中的多功能存储器阵列
公开(公告)号：US06356110B1
公开(公告)日：2002-03-12
申请号：US09675727
申请日：2000-09-29
申请人： Srinivas T. Reddy , Brian D. Johnson , Christopher F. Lane , Ketan H. Zaveri
发明人： Srinivas T. Reddy , Brian D. Johnson , Christopher F. Lane , Ketan H. Zaveri
IPC分类号： H01L2501
CPC分类号： H03K19/1776 , H03K19/17728
摘要： A logic array block (LAB) that is programmably selectively configurable for use as a multifunction memory array is provided. The LAB is configurable for operation in at least two modes: in a first mode, each logic element within the LAB is individually configurable to perform logic functions; in a second mode, the logic elements are collectively usable as a multifunction memory array. The multifunction memory array may be addressed on a LAB-wide basis with separate read and write addresses, such that it may be configured to implement a variety of memory schemes, including first-in-first-out (FIFO) memory and random access memory (RAM).
摘要翻译：提供了可编程选择性地配置用作多功能存储器阵列的逻辑阵列块（LAB）。 LAB可配置为至少两种模式运行：在第一种模式下，LAB内的每个逻辑单元均可单独配置以执行逻辑功能; 在第二模式中，逻辑元件可共同用作多功能存储器阵列。多功能存储器阵列可以在具有单独的读和写地址的基于LAB的基础上寻址，使得其可以被配置为实现各种存储器方案，包括先进先出（FIFO）存储器和随机存取存储器（随机存取存储器）。

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