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1. 发明授权

US06417694B1 Programmable logic device with hierarchical interconnection resources 有权
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06417694B1
公开(公告)日：2002-07-09
申请号：US09956748
申请日：2001-09-19
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。本地导体与每个区域相关联，主要用于使信号进入该区域。在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

2. 发明授权

US6069487A Programmable logic device circuitry for improving multiplier speed and/or efficiency 失效
标题翻译：可编程逻辑器件电路，用于提高乘法器速度和/或效率
公开(公告)号：US6069487A
公开(公告)日：2000-05-30
申请号：US94387
申请日：1998-06-09
申请人： Christopher F. Lane , Srinivas T. Reddy , Richard G. Cliff , Ketan H. Zaveri , Bruce B. Pedersen , Kerry Veenstra
发明人： Christopher F. Lane , Srinivas T. Reddy , Richard G. Cliff , Ketan H. Zaveri , Bruce B. Pedersen , Kerry Veenstra
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17792 , H03K19/17728 , H03K19/17732
摘要： In order to facilitate the performance of multiplications in programmable logic devices, individual logic modules of such devices are constructed so that one logic module can perform (at least) both one place of binary multiplication and one place of full binary addition. This makes it possible to reduce the number of logic modules that are required to perform a multiplication. It also reduces the number of inter-module connections employed in a multiplication, thereby tending to decrease the time required to perform a multiplication.
摘要翻译：为了便于可编程逻辑器件中的乘法性能，这些器件的各个逻辑模块被构造成使得一个逻辑模块可以执行（至少）二进制乘法的一个位置和完全二进制加法的一个位置。这使得可以减少执行乘法所需的逻辑模块的数量。它还减少了乘法中使用的模块间连接的数量，从而倾向于减少执行乘法所需的时间。

3. 发明授权

US08198914B2 Apparatus and methods for adjusting performance of programmable logic devices 有权
标题翻译：用于调节可编程逻辑器件性能的装置和方法
公开(公告)号：US08198914B2
公开(公告)日：2012-06-12
申请号：US13098450
申请日：2011-04-30
申请人： Andy L. Lee , Christopher F. Lane , Ketan H. Zaveri , Richard G. Cliff , Cameron R. McClintock , Srinivas T. Reddy , David Lewis
发明人： Andy L. Lee , Christopher F. Lane , Ketan H. Zaveri , Richard G. Cliff , Cameron R. McClintock , Srinivas T. Reddy , David Lewis
IPC分类号： H01L25/00
CPC分类号： H03K19/17784 , H03K19/17788 , H03K19/17792
摘要： A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.
摘要翻译：可编程逻辑器件（PLD）至少包括两个区域。每个区域包括具有一组晶体管的电路。两个区域中的每一个具有对应的固定晶体管阈值电压，对应的固定晶体管体偏置和相应的固定电源电压。

4. 发明授权

US5977793A Programmable logic device with hierarchical interconnection resources 失效
公开(公告)号：US5977793A
公开(公告)日：1999-11-02
申请号：US855192
申请日：1997-05-13
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H01L21/82 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/1778
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

5. 发明申请

US20110204919A1 Apparatus and methods for adjusting performance of programmable logic devices 有权
公开(公告)号：US20110204919A1
公开(公告)日：2011-08-25
申请号：US13098450
申请日：2011-04-30
申请人： Andy L. Lee , Christopher F. Lane , Ketan H. Zaveri , Richard G. Cliff , Cameron R. McClintock , Srinivas T. Reddy , David Lewis
发明人： Andy L. Lee , Christopher F. Lane , Ketan H. Zaveri , Richard G. Cliff , Cameron R. McClintock , Srinivas T. Reddy , David Lewis
IPC分类号： H03K19/177
CPC分类号： H03K19/17784 , H03K19/17788 , H03K19/17792
摘要： A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.

6. 发明授权

US07936184B2 Apparatus and methods for adjusting performance of programmable logic devices 有权
标题翻译：用于调节可编程逻辑器件性能的装置和方法
公开(公告)号：US07936184B2
公开(公告)日：2011-05-03
申请号：US11361642
申请日：2006-02-24
申请人： Andy L. Lee , Christopher F. Lane , Ketan H. Zaveri , Richard G. Cliff , Cameron R. McClintock , Srinivas T. Reddy , David Lewis
发明人： Andy L. Lee , Christopher F. Lane , Ketan H. Zaveri , Richard G. Cliff , Cameron R. McClintock , Srinivas T. Reddy , David Lewis
IPC分类号： H01L25/00
CPC分类号： H03K19/17784 , H03K19/17788 , H03K19/17792
摘要： A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.
摘要翻译：可编程逻辑器件（PLD）至少包括两个区域。每个区域包括具有一组晶体管的电路。两个区域中的每一个具有对应的固定晶体管阈值电压，对应的固定晶体管体偏置和相应的固定电源电压。

7. 发明授权

US06462577B1 Configurable memory structures in a programmable logic device 有权
标题翻译：可编程逻辑器件中的可配置存储器结构
公开(公告)号：US06462577B1
公开(公告)日：2002-10-08
申请号：US09761608
申请日：2001-01-16
申请人： Andy L. Lee , Christopher F. Lane , Srinivas T. Reddy , Brian D. Johnson , Ketan H. Zaveri , Mario Guzman , Quyen Doan
发明人： Andy L. Lee , Christopher F. Lane , Srinivas T. Reddy , Brian D. Johnson , Ketan H. Zaveri , Mario Guzman , Quyen Doan
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , G11C8/12 , H03K19/17728
摘要： A programmable logic device is provided in which logic array blocks (LABs) may be programmably configured for use as one of a variety of memory structures. The configurable memory structures may have separate read and write addresses, thereby making it possible to implement a variety of memory structures such as FIFO memory, ROM, RAM, and shift-registers.
摘要翻译：提供了一种可编程逻辑器件，其中可编程地将逻辑阵列块（LAB）配置为用作各种存储器结构之一。可配置的存储器结构可以具有单独的读和写地址，从而使得可以实现各种存储器结构，例如FIFO存储器，ROM，RAM和移位寄存器。

8. 发明授权

US07295036B1 Method and system for reducing static leakage current in programmable logic devices 有权
标题翻译：用于减少可编程逻辑器件中的静态漏电流的方法和系统
公开(公告)号：US07295036B1
公开(公告)日：2007-11-13
申请号：US11291712
申请日：2005-11-30
申请人： Ketan H. Zaveri , Christopher F. Lane
发明人： Ketan H. Zaveri , Christopher F. Lane
IPC分类号： H03K19/173
CPC分类号： H03K19/17772 , H03K19/17728 , H03K19/17784
摘要： A programmable logic device having logic block that can be selectively placed in a reduced power consumption mode is provided. The PLD includes a plurality of logic array blocks (LABs) and a plurality of interconnects defining signal pathways between the plurality of LABs. Sleep control logic of the PLD issues a sleep control signal for placing at least a portion of the plurality of LABs in a sleep mode. Bias control logic of the PLD is in communication with the sleep control logic. The bias control logic is triggered by the sleep control signal to issue a first bias control signal and a second bias control signal. The first and second bias control signals are transmitted to corresponding transistors of the LABS. The first and second bias control signals apply a reverse bias to corresponding transistor wells to increase threshold voltages for the respective transistors.
摘要翻译：提供了具有逻辑块的可编程逻辑器件，其可以选择性地放置在降低的功耗模式中。 PLD包括多个逻辑阵列块（LAB）和定义多个LAB之间的信号路径的多个互连。 PLD的休眠控制逻辑发出睡眠控制信号，用于将多个LAB的至少一部分放置在睡眠模式中。 PLD的偏置控制逻辑与睡眠控制逻辑通信。偏置控制逻辑由休眠控制信号触发，以发出第一偏置控制信号和第二偏置控制信号。第一和第二偏置控制信号被传送到LABS的相应晶体管。第一和第二偏置控制信号向对应的晶体管阱施加反向偏置以增加相应晶体管的阈值电压。

9. 发明授权

US06798242B2 Programmable logic device with hierarchical interconnection resources 失效
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06798242B2
公开(公告)日：2004-09-28
申请号：US10426991
申请日：2003-04-29
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。本地导体与每个区域相关联，主要用于使信号进入该区域。在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

10. 发明授权

US06577160B2 Programmable logic device with hierarchical interconnection resources 有权
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06577160B2
公开(公告)日：2003-06-10
申请号：US10170026
申请日：2002-06-10
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region. Local conductors are associated with each region. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联。本地导体与每个区域相关联。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

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