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1. 发明授权

US06826741B1 Flexible I/O routing resources 有权
标题翻译：灵活的I / O路由资源
公开(公告)号：US06826741B1
公开(公告)日：2004-11-30
申请号：US10289629
申请日：2002-11-06
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Triet Nguyen , David Jefferson , Paul Leventis , David Lewis , Vaughn Betz , Michael Chan
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Triet Nguyen , David Jefferson , Paul Leventis , David Lewis , Vaughn Betz , Michael Chan
IPC分类号： G06F1750
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In one aspect, flexible routing resources provided are comprising an arrangement of staggered line segments on a periphery of an electronic device. In another aspect, I/O bus lines a re coupled to receive signals from and to provide signals to other bus lines, core routing, and I/O circuitry, thus facilitating the use of the I/O bus for a variety of routes that may include I/O-to-core, core-to-I/O and core-to-core routes. In another aspect, a length of I/O bus lines is optimized for speed over long signal routes with high fanout. In another aspect, the loading effects of high fanout are minimized by using a plurality of tapping buffers to couple lines to both core routing and to I/O circuitry. In another aspect, a spiraling technique is provided that allows a continuous bus having line segments of consistent length whether or not the number of I/O blocks is an integral multiple of the selected logical length for line segments.
摘要翻译：在一个方面，提供的灵活路由资源包括在电子设备的外围上的交错线段的布置。在另一方面，I / O总线线路被耦合以从其接收信号并向其它总线线路，核心路由和I / O电路提供信号，从而便于将I / O总线用于各种路由，可能包括I / O到核心，核到I / O和核心到核心的路由。在另一方面，I / O总线的长度针对具有高扇出的长信号路由的速度被优化。在另一方面，通过使用多个分接缓冲器来将线耦合到核心路由和I / O电路两者，高扇出的负载效应被最小化。在另一方面，提供一种螺旋式技术，其允许具有一致长度的线段的连续总线，无论I / O块的数量是否为线段的所选逻辑长度的整数倍。

2. 发明授权

US06965249B2 Programmable logic device with redundant circuitry 失效
标题翻译：具有冗余电路的可编程逻辑器件
公开(公告)号：US06965249B2
公开(公告)日：2005-11-15
申请号：US10159581
申请日：2002-05-30
申请人： Christopher Lane , Ketan Zaveri , Hyun Yi , Giles Powell , Paul Leventis , David Jefferson , David Lewis , Triet Nguyen , Vikram Santurkar , Michael Chan , Andy Lee , Brian Johnson , David Cashman
发明人： Christopher Lane , Ketan Zaveri , Hyun Yi , Giles Powell , Paul Leventis , David Jefferson , David Lewis , Triet Nguyen , Vikram Santurkar , Michael Chan , Andy Lee , Brian Johnson , David Cashman
IPC分类号： H01L21/82 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/17736 , H03K19/17744
摘要： A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.
摘要翻译：可编程逻辑器件和相关方法提供有可修复区域。在一个方面，一般布线互连线在可修复区域内被分段。在另一方面，提供IO总线线路和相关电路，其适应交错分段结构中的冗余。在另一方面，特定逻辑区域之间的专用路由架构适应移位以限定和利用可修复区域。在本发明的方面的几个示例性实施例的上下文中示出和描述了其它方面的原理。

3. 发明授权

US07228451B1 Programmable clock network for distributing clock signals to and between first and second sections of an integrated circuit 有权
标题翻译：可编程时钟网络，用于将时钟信号分配到集成电路的第一和第二部分之间和之间
公开(公告)号：US07228451B1
公开(公告)日：2007-06-05
申请号：US11270801
申请日：2005-11-08
申请人： Triet Nguyen , David Jefferson , Srinivas Reddy , Keone Streicher
发明人： Triet Nguyen , David Jefferson , Srinivas Reddy , Keone Streicher
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A clock network for an integrated circuits includes a first set of lines configured to distribute clock signals to a first section of the integrated circuit. The clock network also includes a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit.
摘要翻译：用于集成电路的时钟网络包括被配置为将时钟信号分配给集成电路的第一部分的第一组线路。时钟网络还包括第二组线路，其被配置为将时钟信号分配给集成电路的第一部分与集成电路的第二部分分开。

4. 发明授权

US06996736B1 Programmable clock network for distributing clock signals to and between first and second sections of an integrated circuit 有权
标题翻译：可编程时钟网络，用于将时钟信号分配到集成电路的第一和第二部分之间和之间
公开(公告)号：US06996736B1
公开(公告)日：2006-02-07
申请号：US10076172
申请日：2002-02-12
申请人： Triet Nguyen , David Jefferson , Srinivas Reddy , Keone Streicher
发明人： Triet Nguyen , David Jefferson , Srinivas Reddy , Keone Streicher
IPC分类号： G06F1/10
CPC分类号： G06F1/10
摘要： A clock network for an integrated circuits includes a first set of lines configured to distribute clock signals to a first section of the integrated circuit. The clock network also includes a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit.
摘要翻译：用于集成电路的时钟网络包括被配置为将时钟信号分配给集成电路的第一部分的第一组线路。时钟网络还包括第二组线路，其被配置为将时钟信号分配给集成电路的第一部分与集成电路的第二部分分开。

5. 发明授权

US06759871B2 Line segmentation in programmable logic devices having redundancy circuitry 有权
标题翻译：具有冗余电路的可编程逻辑器件中的线分割
公开(公告)号：US06759871B2
公开(公告)日：2004-07-06
申请号：US10422007
申请日：2003-04-22
申请人： Triet Nguyen , Changsong Zhang , David Jefferson
发明人： Triet Nguyen , Changsong Zhang , David Jefferson
IPC分类号： H03K19177
CPC分类号： H03K19/17764 , G11C29/70 , H03K19/17728 , H03K19/17736
摘要： Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.
摘要翻译：用于在具有冗余电路的可编程逻辑器件中分割线路的方法和装置。可编程逻辑器件包括第一多个逻辑阵列块。第一多个逻辑阵列块包括第一逻辑阵列块和第二逻辑阵列块，耦合到分段缓冲器的第一可编程互连线并且可编程地耦合到第一逻辑阵列块，以及耦合到分段的第二可编程互连线缓冲器并且可编程地耦合到第二逻辑阵列块。分段缓冲器能够选择性地在第一可编程互连线和第二可编程互连线之间提供开路，缓冲器驱动从第一可编程互连线到第二可编程互连线的信号，或者来自第二可编程互连线的缓冲器驱动信号互连线到第一可编程互连线。

6. 发明授权

US06600337B2 Line segmentation in programmable logic devices having redundancy circuitry 有权
公开(公告)号：US06600337B2
公开(公告)日：2003-07-29
申请号：US09844077
申请日：2001-04-26
申请人： Triet Nguyen , Changsong Zhang , David Jefferson
发明人： Triet Nguyen , Changsong Zhang , David Jefferson
IPC分类号： H03K19177
CPC分类号： H03K19/17764 , G11C29/70 , H03K19/17728 , H03K19/17736
摘要： Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.

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