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1. 发明授权

US6100175A Method and apparatus for aligning and attaching balls to a substrate 有权
公开(公告)号：US6100175A
公开(公告)日：2000-08-08
申请号：US143631
申请日：1998-08-28
申请人： Alan G. Wood , Salman Akram , Mike Hess , David R. Hembree
发明人： Alan G. Wood , Salman Akram , Mike Hess , David R. Hembree
IPC分类号： H01L21/48 , H05K3/34 , H01L21/44
CPC分类号： H05K3/3478 , H01L21/4853 , H01L24/742 , H01L2224/11003 , H01L2224/11334 , H01L2224/4824 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H05K2203/041 , H05K2203/082 , Y10S438/975
摘要： A method for aligning and bonding balls to substrates, such as semiconductor wafers, dice and packages, is provided. The method employs a ball retaining plate having a pattern of micromachined cavities and vacuum conduits for retaining the balls. In addition, a substrate alignment member attached to the ball retaining plate, aligns the substrate to the balls. Using the substrate alignment member, bonding sites on the substrate can be placed in physical contact with the balls which are held by vacuum on the ball retaining plate. Next, the ball alignment plate and substrate can be place in a furnace for reflowing and bonding the balls to the bonding sites. An apparatus for performing the method includes the ball retaining plate and the substrate alignment member. A system for performing the method includes a ball loader mechanism for loading balls onto the ball retaining plate, and a vacuum fixture for applying a vacuum to the ball retaining cavities.

2. 发明授权

US06364196B1 Method and apparatus for aligning and attaching balls to a substrate 失效
标题翻译：用于将球对准和附着到基底的方法和装置
公开(公告)号：US06364196B1
公开(公告)日：2002-04-02
申请号：US09519583
申请日：2000-03-06
申请人： Alan G. Wood , Salman Akram , Mike Hess , David R. Hembree
发明人： Alan G. Wood , Salman Akram , Mike Hess , David R. Hembree
IPC分类号： B23K100
CPC分类号： H05K3/3478 , H01L21/4853 , H01L24/742 , H01L2224/11003 , H01L2224/11334 , H01L2224/4824 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H05K2203/041 , H05K2203/082 , Y10S438/975 , H01L2924/00 , H01L2224/0401
摘要： A method for aligning and bonding balls to substrates, such as semiconductor wafers, dice and packages, is provided. The method employs a ball retaining plate having a pattern of micromachined cavities and vacuum conduits for retaining the balls. In addition, a substrate alignment member attached to the ball retaining plate, aligns the substrate to the balls. Using the substrate alignment member, bonding sites on the substrate can be placed in physical contact with the balls which are held by vacuum on the ball retaining plate. Next, the ball alignment plate and substrate can be place in a furnace for reflowing and bonding the balls to the bonding sites. An apparatus for performing the method includes the ball retaining plate and the substrate alignment member. A system for performing the method includes a ball loader mechanism for loading balls onto the ball retaining plate, and a vacuum fixture for applying a vacuum to the ball retaining cavities.
摘要翻译：提供了用于将球对准和结合到诸如半导体晶片，骰子和封装之类的衬底的方法。该方法采用具有微加工空腔图案的球保持板和用于保持球的真空管道。此外，附接到球保持板的基板对准部件将基板对准球。使用基板对准部件，可以将基板上的接合部位与通过真空保持在球保持板上的球物理接触。接下来，可以将球定位板和基板放置在炉中以将球回弹并结合到结合位置。用于执行该方法的装置包括球保持板和基板对准构件。用于执行该方法的系统包括用于将球装载到球保持板上的球加载机构，以及用于向球保持腔施加真空的真空夹具。

3. 发明授权

US07709776B2 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers 有权
标题翻译：具有光学器件的微电子成像器和制造这种微电子成像器的方法
公开(公告)号：US07709776B2
公开(公告)日：2010-05-04
申请号：US12390195
申请日：2009-02-20
申请人： Warren M. Farnworth , Sidney B. Rigg , William Mark Hiatt , Alan G. Wood , Peter A. Benson , James M. Wark , David R. Hembree , Kyle K. Kirby , Charles M. Watkins , Salman Akram
发明人： Warren M. Farnworth , Sidney B. Rigg , William Mark Hiatt , Alan G. Wood , Peter A. Benson , James M. Wark , David R. Hembree , Kyle K. Kirby , Charles M. Watkins , Salman Akram
IPC分类号： H01L27/00 , H01L31/0232
CPC分类号： H01L27/00 , B33Y80/00 , H01L27/14618 , H01L27/14625 , H01L27/14683 , H01L27/14687 , H01L2224/48091 , H01L2224/48227 , H01L2924/01077 , H01L2924/01078 , H01L2924/00014
摘要： Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.
摘要翻译：微电子成像器组件包括包括衬底的工件和在衬底上和/或衬底中的多个成像管芯。基板包括前侧和后侧，并且成像管芯包括在基板的前侧的成像传感器和可操作地耦合到图像传感器的外部触点。微电子成像器组件还包括相对于成像管芯叠加的光学支架。光学支撑件可以直接在基板上或衬底上的盖上。单个光学支撑件可以具有（a）与图像传感器中的一个对准的开口，以及（b）与图像传感器相距一定距离处的轴承元件。微电子成像器组件还可以包括由光学器件支撑件安装或以其它方式承载的光学器件。

4. 发明申请

US20090155949A1 MICROELECTRONIC IMAGERS WITH OPTICAL DEVICES AND METHODS OF MANUFACTURING SUCH MICROELECTRONIC IMAGERS 有权
标题翻译：具有光学器件的微电子成像器和制造这种微电子成像器的方法
公开(公告)号：US20090155949A1
公开(公告)日：2009-06-18
申请号：US12390195
申请日：2009-02-20
申请人： Warren M. Farnworth , Sidney B. Rigg , William Mark Hiatt , Alan G. Wood , Peter A. Benson , James M. Wark , David R. Hembree , Kyle K. Kirby , Charles M. Watkins , Salman Akram
发明人： Warren M. Farnworth , Sidney B. Rigg , William Mark Hiatt , Alan G. Wood , Peter A. Benson , James M. Wark , David R. Hembree , Kyle K. Kirby , Charles M. Watkins , Salman Akram
IPC分类号： H01L31/0232
CPC分类号： H01L27/00 , B33Y80/00 , H01L27/14618 , H01L27/14625 , H01L27/14683 , H01L27/14687 , H01L2224/48091 , H01L2224/48227 , H01L2924/01077 , H01L2924/01078 , H01L2924/00014
摘要： Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.
摘要翻译：微电子成像器组件包括包括衬底的工件和在衬底上和/或衬底中的多个成像管芯。基板包括前侧和后侧，并且成像管芯包括在基板的前侧的成像传感器和可操作地耦合到图像传感器的外部触点。微电子成像器组件还包括相对于成像管芯叠加的光学支架。光学支撑件可以直接在基板上或衬底上的盖上。单个光学支撑件可以具有（a）与图像传感器中的一个对准的开口，以及（b）与图像传感器相距一定距离处的轴承元件。微电子成像器组件还可以包括由光学器件支撑件安装或以其它方式承载的光学器件。

5. 发明授权

US07250780B2 Probe card for semiconductor wafers having mounting plate and socket 失效
标题翻译：带安装板和插座的半导体晶圆探头卡
公开(公告)号：US07250780B2
公开(公告)日：2007-07-31
申请号：US10742729
申请日：2003-12-19
申请人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
发明人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
IPC分类号： G01R1/073 , G01R31/28
CPC分类号： G01R31/2886
摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.
摘要翻译：提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。探针卡被配置用于与测试电路电气通信的常规测试装置，例如晶片探测器处理器。探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。互连衬底可以由具有穿透突起的凸起接触构件的硅形成。或者，接触构件可以形成为用于测试凸起的晶片的凹陷。膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

6. 发明授权

US06392429B1 Temporary semiconductor package having dense array external contacts 失效
标题翻译：具有密集阵列外部触点的临时半导体封装
公开(公告)号：US06392429B1
公开(公告)日：2002-05-21
申请号：US09594748
申请日：2000-06-14
申请人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Salman Akram
发明人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Salman Akram
IPC分类号： G01R3102
CPC分类号： H01L23/49838 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/0735 , G01R3/00 , G01R31/2863 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L24/80 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2225/06562 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H01L2224/05599
摘要： A temporary package for a semiconductor die is provided. The temporary package has an outline and external contact configuration that are the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. The package includes a base, an interconnect and a force applying mechanism. The package base includes external contacts formed in a dense array, such as a land grid array (LGA), a pin grid array (PGA), a bumped grid array (BGA) or a perimeter array. The package base can be formed of ceramic or plastic with internal conductive lines using a ceramic lamination process, a 3-D molding process or a Cerdip formation process.
摘要翻译：提供了一种用于半导体管芯的临时封装。临时包装具有与常规塑料或陶瓷半导体封装相同的轮廓和外部接触构造。临时包装可用于使用标准设备对模具进行老化测试。然后可以将模具从包装中取出并被认证为已知的好的模具。该包装包括底座，互连和力施加机构。封装基座包括形成在密集阵列中的外部触头，例如焊盘格栅阵列（LGA），引脚格栅阵列（PGA），凸起栅格阵列（BGA）或周边阵列。封装基底可以由具有内部导电线的陶瓷或塑料形成，使用陶瓷层压工艺，3-D成型工艺或Cerdip形成工艺。

7. 发明授权

US06313651B1 Carrier and system for testing bumped semiconductor components 失效
标题翻译：用于测试碰撞半导体元件的载体和系统
公开(公告)号：US06313651B1
公开(公告)日：2001-11-06
申请号：US09322724
申请日：1999-05-28
申请人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , Salman Akram
发明人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , Salman Akram
IPC分类号： G01R3102
CPC分类号： G01R1/0483 , H01L2224/0401 , H01L2224/05552 , H01L2224/48091 , H01L2224/81385 , H01L2924/01021 , H01L2924/01087 , H01L2924/09701 , H01L2924/10155 , H01L2924/15311 , H01L2924/00014
摘要： A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.
摘要翻译：提供了一种半导体载体和系统，用于测试具有接触凸块的凸起的半导体部件，例如芯片和封装。载体包括基底，互连和力施加机构。互连包括适于电接触接触凸块的接触构件的图案。互连可以包括具有形成为凹陷的接触构件的衬底，或者作为突出部的覆盖有导电层的衬底。或者，互连可以是直接结合到载体的基底的多层带。除了提供电连接之外，接触构件通过使接触构件内的接触凸块自对中来执行对准功能。载体还可以包括配置成将部件与互连对准的对准部件。该系统可以包括载体，插座和诸如与测试电路电连接的老化板的测试装置。

8. 发明授权

US06255833B1 Method for testing semiconductor dice and chip scale packages 失效
标题翻译：半导体芯片和芯片级封装的测试方法
公开(公告)号：US06255833B1
公开(公告)日：2001-07-03
申请号：US09098594
申请日：1998-06-17
申请人： Salman Akram , Alan G. Wood , David R. Hembree , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , David R. Hembree , Warren M. Farnworth
IPC分类号： G01R3102
CPC分类号： G01R1/0483 , H01L2224/48091 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/30107 , H01L2924/00014
摘要： A method and carrier for testing semiconductor dice such as bare dice or chip scale packages are provided. The carrier includes a base for retaining a single die, an interconnect for establishing temporary electrical communication with the die, and a force applying mechanism for biasing the die and interconnect together. In an illustrative embodiment the base includes conductors arranged in a universal pattern adapted to electrically connect to different sized interconnects. Interconnects are thus interchangeable on a base for testing different types of dice using the same base. The conductors on the base can be formed on a planar active surface of the base or on a stepped active surface having different sized cavities for mounting different sized interconnects. In an alternate embodiment the carrier includes an interposer. In a first interposer embodiment, the interposer connects directly to external test circuitry and can be changed to accommodate different sized interconnects. In a second interposer embodiment, the interposer connects to conductors on the base and adapts the base for use with different sized interconnects.
摘要翻译：提供了用于测试半导体裸片（例如裸裸片或芯片级封装）的方法和载体。载体包括用于保持单个管芯的基座，用于建立与管芯的临时电连通的互连件，以及用于偏压管芯并互连在一起的施力机构。在说明性实施例中，底座包括以适于电连接到不同尺寸的互连件的通用图案布置的导体。因此，互连在基座上可以互换，用于使用相同的基底测试不同类型的骰子。基座上的导体可以形成在基座的平面有源表面上或具有不同尺寸的空腔的阶梯式有源表面上，用于安装不同尺寸的互连。在替代实施例中，载体包括插入器。在第一插入器实施例中，插入器直接连接到外部测试电路，并且可以改变以适应不同尺寸的互连。在第二插入器实施例中，插入器连接到基座上的导体，并使基座适配于不同大小的互连使用。

9. 发明授权

US6064216A Apparatus for testing semiconductor wafers 有权
标题翻译：半导体晶片测试装置
公开(公告)号：US6064216A
公开(公告)日：2000-05-16
申请号：US241553
申请日：1999-02-01
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood , David R. Hembree , James M. Wark , John O. Jacobson
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood , David R. Hembree , James M. Wark , John O. Jacobson
IPC分类号： G01R1/04 , G01R31/28 , G01R31/02
CPC分类号： G01R1/0491 , G01R31/2886
摘要： A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.
摘要翻译：提供了一种用于测试半导体晶片的方法，装置和系统。该方法包括提供晶片载体以提供用于接收和传输测试信号到晶片的电路径。晶片载体包括用于保持晶片的基座和具有被配置为与晶片上的接触位置建立电连通的接触构件的互连。晶片载体可以包括被配置为偏置晶片并在组装的载体中互连在一起的一个或多个可压缩弹簧构件。可以使用光学对准技术来组装晶片载体，其中晶片与互连对准，以及类似于用于倒装芯片接合半导体晶片的对准器焊接工具的组装工具。与载体一起使用的系统可以包括测试装置，其被配置为在晶片受到温度循环的同时将测试信号通过载体施加到晶片。

10. 发明授权

US5915977A System and interconnect for making temporary electrical connections with bumped semiconductor components 有权
标题翻译：用于与凸起的半导体部件进行临时电连接的系统和互连
公开(公告)号：US5915977A
公开(公告)日：1999-06-29
申请号：US138612
申请日：1998-08-24
申请人： David R. Hembree , John O. Jacobson , James M. Wark , Warren M. Farnworth , Salman Akram , Alan G. Wood
发明人： David R. Hembree , John O. Jacobson , James M. Wark , Warren M. Farnworth , Salman Akram , Alan G. Wood
IPC分类号： G01R1/04 , H01L21/00 , H01R12/04 , H05K3/32 , H01R9/09
CPC分类号： H01L21/67144 , G01R1/0408 , H05K3/326 , H01L2224/1601 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2224/81385
摘要： An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.
摘要翻译：提供了一种用于与具有接触凸块的半导体部件建立临时电连通的互连和系统。互连包括具有适于电接触接触凸块的接触部件图案的基板。衬底可由诸如陶瓷，硅，FR-4或光刻化学可加工玻璃的材料形成。接触构件可以形成为覆盖有与衬底上的导体和端子触点电连通的导电层的凹陷。或者，接触构件可以形成为适于穿透接触凸块的突起，作为具有粗糙纹理表面的微胶囊，或者形成为具有凹陷的沉积层。互连可以用于晶片级测试系统中，用于测试包含在晶片上的骰子，或者用于测试裸露的骰子或凸起的芯片级封装的芯片级测试系统。

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