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1. 发明授权

US07250780B2 Probe card for semiconductor wafers having mounting plate and socket 失效
标题翻译：带安装板和插座的半导体晶圆探头卡
公开(公告)号：US07250780B2
公开(公告)日：2007-07-31
申请号：US10742729
申请日：2003-12-19
申请人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
发明人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
IPC分类号： G01R1/073 , G01R31/28
CPC分类号： G01R31/2886
摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.
摘要翻译：提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。探针卡被配置用于与测试电路电气通信的常规测试装置，例如晶片探测器处理器。探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。互连衬底可以由具有穿透突起的凸起接触构件的硅形成。或者，接触构件可以形成为用于测试凸起的晶片的凹陷。膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

2. 发明授权

US6060891A Probe card for semiconductor wafers and method and system for testing wafers 失效
标题翻译：半导体晶圆探针卡及晶圆测试方法及系统
公开(公告)号：US6060891A
公开(公告)日：2000-05-09
申请号：US797719
申请日：1997-02-11
申请人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
发明人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
IPC分类号： G01R1/073 , G01R31/28
CPC分类号： G01R1/073 , G01R31/2886
摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.
摘要翻译：提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。探针卡被配置用于与测试电路电连通的常规测试装置，例如晶片探测器处理器。探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。互连衬底可以由具有穿透突起的凸起接触构件的硅形成。或者，接触构件可以形成为用于测试凸起的晶片的凹陷。膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

3. 发明授权

US06798224B1 Method for testing semiconductor wafers 失效
标题翻译：半导体晶圆测试方法
公开(公告)号：US06798224B1
公开(公告)日：2004-09-28
申请号：US10072734
申请日：2002-02-05
申请人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
发明人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
IPC分类号： G01R1073
CPC分类号： G01R31/2886
摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.
摘要翻译：提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。探针卡被配置用于与测试电路电连通的常规测试装置，例如晶片探测器处理器。探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。互连衬底可以由具有穿透突起的凸起接触构件的硅形成。或者，接触构件可以形成为用于测试凸起的晶片的凹陷。膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

4. 发明授权

US06359456B1 Probe card and test system for semiconductor wafers 失效
标题翻译：半导体晶圆探针卡和测试系统
公开(公告)号：US06359456B1
公开(公告)日：2002-03-19
申请号：US09929388
申请日：2001-08-14
申请人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
发明人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
IPC分类号： G01R1073
CPC分类号： G01R1/073 , G01R31/2886
摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.
摘要翻译：提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。探针卡被配置用于与测试电路电连通的常规测试装置，例如晶片探测器处理器。探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。互连衬底可以由具有穿透突起的凸起接触构件的硅形成。或者，接触构件可以形成为用于测试凸起的晶片的凹陷。膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

5. 发明授权

US06275052B1 Probe card and testing method for semiconductor wafers 有权
标题翻译：半导体晶圆的探针卡和测试方法
公开(公告)号：US06275052B1
公开(公告)日：2001-08-14
申请号：US09303367
申请日：1999-04-30
申请人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
发明人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
IPC分类号： G01R1073
CPC分类号： G01R1/073 , G01R31/2886
摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.
摘要翻译：提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。探针卡被配置用于与测试电路电连通的常规测试装置，例如晶片探测器处理器。探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。互连衬底可以由具有穿透突起的凸起接触构件的硅形成。或者，接触构件可以形成为用于测试凸起的晶片的凹陷。膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

6. 发明授权

US06419844B1 Method for fabricating calibration target for calibrating semiconductor wafer test systems 失效
标题翻译：制造用于校准半导体晶片测试系统的校准目标的方法
公开(公告)号：US06419844B1
公开(公告)日：2002-07-16
申请号：US09469339
申请日：1999-12-20
申请人： Andrew J. Krivy , Warren M. Farnworth , David R. Hembree , Salman Akram , James M. Wark , John O. Jacobson
发明人： Andrew J. Krivy , Warren M. Farnworth , David R. Hembree , Salman Akram , James M. Wark , John O. Jacobson
IPC分类号： H01L2100
CPC分类号： G01R35/005 , G01R1/073 , Y10T29/49197
摘要： A calibration target for calibrating semiconductor wafer test systems including probe testers and probe card analyzers is provided. Also provided are calibration methods using the calibration target, and a method for fabricating the calibration target. The calibration target includes a substrate with various three dimensional alignment features formed thereon. A first type of alignment feature includes a contrast layer and an alignment fiducial formed on a tip portion thereof. The contrast layer and alignment fiducial are configured for viewing by a viewing device of the probe card analyzer, or the test system, to achieve X-direction and Y-direction calibration. A second type of alignment feature includes a conductive layer formed on a tip portion thereof, which is configured to electrically engage a contact on a check plate of the probe card analyzer, or a probe contact on a probe card of the test system, to achieve Z-direction calibration. The alignment features can be formed by forming raised members on a silicon substrate, and depositing and etching metal layers on the raised members.
摘要翻译：提供了用于校准包括探针测试仪和探针卡分析仪在内的半导体晶片测试系统的校准目标。还提供了使用校准目标的校准方法以及用于制造校准目标的方法。校准目标包括其上形成有各种三维对准特征的基板。第一类型的对准特征包括形成在其顶端部分上的对比层和对准基准。对比层和对准基准被配置为通过探针卡分析仪或测试系统的观察装置进行观察，以实现X方向和Y方向校准。第二类型的对准特征包括形成在其尖端部分上的导电层，其被配置为与探针卡分析器的支撑板上的触点或测试系统的探针卡上的探针接触电接合，以实现 Z向校准。对准特征可以通过在硅衬底上形成凸起构件，以及在凸起构件上沉积和蚀刻金属层来形成。

7. 发明授权

US06420892B1 Calibration target for calibrating semiconductor wafer test systems 有权
标题翻译：用于校准半导体晶圆测试系统的校准目标
公开(公告)号：US06420892B1
公开(公告)日：2002-07-16
申请号：US09685132
申请日：2000-10-10
申请人： Andrew J. Krivy , Warren M. Farnworth , David R. Hembree , Salman Akram , James M. Wark , John O. Jacobson
发明人： Andrew J. Krivy , Warren M. Farnworth , David R. Hembree , Salman Akram , James M. Wark , John O. Jacobson
IPC分类号： G01R3102
CPC分类号： G01R35/005 , G01R1/073 , Y10T29/49197
摘要： A calibration target for calibrating semiconductor wafer test systems including probe testers and probe card analyzers is provided. Also provided are calibration methods using the calibration target, and a method for fabricating the calibration target. The calibration target includes a substrate with various three dimensional alignment features formed thereon. A first type of alignment feature includes a contrast layer and an alignment fiducial formed on a tip portion thereof. The contrast layer and alignment fiducial are configured for viewing by a viewing device of the probe card analyzer, or the test system, to achieve X-direction and Y-direction calibration. A second type of alignment feature includes a conductive layer formed on a tip portion thereof, which is configured to electrically engage a contact on a check plate of the probe card analyzer, or a probe contact on a probe card of the test system, to achieve Z-direction calibration. The alignment features can be formed by forming raised members on a silicon substrate, and depositing and etching metal layers on the raised members.
摘要翻译：提供了用于校准包括探针测试仪和探针卡分析仪在内的半导体晶片测试系统的校准目标。还提供了使用校准目标的校准方法以及用于制造校准目标的方法。校准目标包括其上形成有各种三维对准特征的基板。第一类型的对准特征包括形成在其顶端部分上的对比层和对准基准。对比层和对准基准被配置为通过探针卡分析仪或测试系统的观察装置进行观察，以实现X方向和Y方向校准。第二类型的对准特征包括形成在其尖端部分上的导电层，其被配置为与探针卡分析器的支撑板上的触点或测试系统的探针卡上的探针接触电接合，以实现 Z方向校准。对准特征可以通过在硅衬底上形成凸起构件，以及在凸起构件上沉积和蚀刻金属层来形成。

8. 发明授权

US06239590B1 Calibration target for calibrating semiconductor wafer test systems 失效
标题翻译：用于校准半导体晶圆测试系统的校准目标
公开(公告)号：US06239590B1
公开(公告)日：2001-05-29
申请号：US09084732
申请日：1998-05-26
申请人： Andrew J. Krivy , Warren M. Farnworth , David R. Hembree , Salman Akram , James M. Wark , John O. Jacobson
发明人： Andrew J. Krivy , Warren M. Farnworth , David R. Hembree , Salman Akram , James M. Wark , John O. Jacobson
IPC分类号： G01R104
CPC分类号： G01R35/005 , G01R1/073 , Y10T29/49197
摘要： A calibration target for calibrating semiconductor wafer test systems including probe testers and probe card analyzers is provided. Also provided are calibration methods using the calibration target, and a method for fabricating the calibration target. The calibration target includes a substrate with various three dimensional alignment features formed thereon. A first type of alignment feature includes a contrast layer and an alignment fiducial formed on a tip portion thereof. The contrast layer and alignment fiducial are configured for viewing by a viewing device of the probe card analyzer, or the test system, to achieve X-direction and Y-direction calibration. A second type of alignment feature includes a conductive layer formed on a tip portion thereof, which is configured to electrically engage a contact on a check plate of the probe card analyzer, or a probe contact on a probe card of the test system, to achieve Z-direction calibration. The alignment features can be formed by forming raised members on a silicon substrate, and depositing and etching metal layers on the raised members.
摘要翻译：提供了用于校准包括探针测试仪和探针卡分析仪在内的半导体晶片测试系统的校准目标。还提供了使用校准目标的校准方法以及用于制造校准目标的方法。校准目标包括其上形成有各种三维对准特征的基板。第一类型的对准特征包括形成在其顶端部分上的对比层和对准基准。对比层和对准基准被配置为通过探针卡分析仪或测试系统的观察装置进行观察，以实现X方向和Y方向校准。第二类型的对准特征包括形成在其尖端部分上的导电层，其被配置为与探针卡分析器的支撑板上的触点或测试系统的探针卡上的探针接触电接合，以实现 Z方向校准。对准特征可以通过在硅衬底上形成凸起构件，以及在凸起构件上沉积和蚀刻金属层来形成。

9. 发明授权

US06246245B1 Probe card, test method and test system for semiconductor wafers 失效
标题翻译：半导体晶圆的探针卡，测试方法和测试系统
公开(公告)号：US06246245B1
公开(公告)日：2001-06-12
申请号：US09027880
申请日：1998-02-23
申请人： Salman Akram , C. Patrick Doherty , Warren M. Farnworth , David R. Hembree
发明人： Salman Akram , C. Patrick Doherty , Warren M. Farnworth , David R. Hembree
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , G01R1/07378
摘要： A probe card for testing a semiconductor wafer, a test method, and a test system employing the probe card are provided. The probe card includes: a substrate; patterns of pin contacts slidably mounted to the substrate; and a force applying member for biasing the pin contacts into electrical contact with die contacts on the wafer. In an illustrative embodiment the force applying member includes spring loaded electrical connectors in physical and electrical contact with the pin contacts. Alternately, the force applying member includes a compressible pad for multiple pin contacts, or separate compressible pads for each pin contact. A penetration depth of the pin contacts into the die contacts is controlled by selecting a spring force of the force applying member, and an amount of Z-direction overdrive of the pin contacts into the die contacts.
摘要翻译：提供了用于测试半导体晶片的探针卡，测试方法和采用探针卡的测试系统。探针卡包括：基底; 引脚触点的图案可滑动地安装到基板上; 以及用于使所述销触点偏压以与所述晶片上的芯片触点电接触的施力部件。在示例性实施例中，施力构件包括与销触点物理和电接触的弹簧加载的电连接器。或者，施力构件包括用于多个针接触的可压缩垫，或者每个销接触的单独的可压缩垫。通过选择力施加部件的弹簧力来控制销接触到模具接触部中的穿透深度，并且销的Z方向过驱动量接触到模具接触件中。

10. 发明授权

US06356098B1 Probe card, test method and test system for semiconductor wafers 失效
标题翻译：半导体晶圆的探针卡，测试方法和测试系统
公开(公告)号：US06356098B1
公开(公告)日：2002-03-12
申请号：US09394960
申请日：1999-09-10
申请人： Salman Akram , C. Patrick Doherty , Warren M. Farnworth , David R. Hembree
发明人： Salman Akram , C. Patrick Doherty , Warren M. Farnworth , David R. Hembree
IPC分类号： G01R3126
CPC分类号： G01R31/2886 , G01R1/07378
摘要： A probe card for testing a semiconductor wafer, a test method, and a test system employing the probe card are provided. The probe card includes: a substrate; patterns of pin contacts slidably mounted to the substrate; and a force applying member for biasing the pin contacts into electrical contact with die contacts on the wafer. In an illustrative embodiment the force applying member includes spring loaded electrical connectors in physical and electrical contact with the pin contacts. Alternately, the force applying member includes a compressible pad for multiple pin contacts, or separate compressible pads for each pin contact. A penetration depth of the pin contacts into the die contacts is controlled by selecting a spring force of the force applying member, and an amount of Z-direction overdrive of the pin contacts into the die contacts.
摘要翻译：提供了用于测试半导体晶片的探针卡，测试方法和采用探针卡的测试系统。探针卡包括：基底; 引脚触点的图案可滑动地安装到基板上; 以及用于使所述销触点偏压以与所述晶片上的芯片触点电接触的施力部件。在示例性实施例中，施力构件包括与销触点物理和电接触的弹簧加载的电连接器。或者，施力构件包括用于多个针接触的可压缩垫，或者每个销接触的单独的可压缩垫。通过选择力施加部件的弹簧力来控制销接触到模具接触部中的穿透深度，并且销的Z方向过驱动量接触到模具接触件中。

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