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1. 发明授权

US08785271B2 DRAM cell based on conductive nanochannel plate 有权
标题翻译：基于导电纳米通道板的DRAM单元
公开(公告)号：US08785271B2
公开(公告)日：2014-07-22
申请号：US13017682
申请日：2011-01-31
申请人： Dmytro Chumakov , Wolfgang Buchholtz , Petra Hetzer
发明人： Dmytro Chumakov , Wolfgang Buchholtz , Petra Hetzer
IPC分类号： H01L21/8242
CPC分类号： H01L27/1082 , B82Y10/00 , H01L27/10852 , H01L28/90
摘要： A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask.
摘要翻译：在导电体中的纳米通道中形成电容器。实施例包括通过第一层间电介质（ILD）形成源极接触，在第一ILD上形成导电体，在导电体上形成第二ILD，通过第二ILD，导电体和第一ILD形成漏极和栅极接触在导电体中形成纳米通道，在通道中形成绝缘层，并使通道金属化。一个实施方案包括通过在第二ILD上形成掩模形成纳米通道，该掩模具有50纳米（nm）至100nm的间距的特征，通过掩模蚀刻第二ILD，通过掩模将导电体蚀刻到深度为导电体的厚度的80％至90％，并且去除掩模。

2. 发明申请

US20100243903A1 METHOD AND SYSTEM FOR MATERIAL CHARACTERIZATION IN SEMICONDUCTOR PRODUCTION PROCESSES BASED ON FTIR WITH VARIABLE ANGLE OF INCIDENCE 审中-公开
标题翻译：基于具有可变角度的FTIR的半导体生产过程中的材料特性的方法和系统
公开(公告)号：US20100243903A1
公开(公告)日：2010-09-30
申请号：US12728582
申请日：2010-03-22
申请人： Torsten Fahr , Matthias Schaller , Wolfgang Buchholtz
发明人： Torsten Fahr , Matthias Schaller , Wolfgang Buchholtz
IPC分类号： G01N21/27 , G01N21/84
CPC分类号： G01N21/55 , G01J3/453 , G01N21/3563 , G01N2021/3595
摘要： During the processing of complex semiconductor devices, dielectric material systems comprising a patterned structure may be analyzed in a non-destructive manner by using an FTIR technique in combination with a plurality of angles of incidence. In this manner, topography-related information may be obtained and/or data analysis may be made more efficient due to the increased amount of information obtained by the plurality of angles of incidence.
摘要翻译：在复杂半导体器件的处理期间，可以通过使用与多个入射角相结合的FTIR技术以非破坏性方式分析包括图案化结构的电介质材料系统。以这种方式，由于通过多个入射角获得的信息量的增加，可以获得与/或数据分析更有效的地形相关信息。

3. 发明申请

US20080099794A1 SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN 有权
标题翻译：包含用于创建拉伸和压缩应变的嵌入式SI / GE材料的NMOS和PMOS晶体管的半导体器件
公开(公告)号：US20080099794A1
公开(公告)日：2008-05-01
申请号：US11748902
申请日：2007-05-15
申请人： Sven Beyer , Manfred Horstmann , Patrick Press , Wolfgang Buchholtz
发明人： Sven Beyer , Manfred Horstmann , Patrick Press , Wolfgang Buchholtz
IPC分类号： H01L29/04 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/165 , H01L29/66621 , H01L29/66651 , H01L29/7833 , H01L29/7848 , H01L29/7849
摘要： By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.
摘要翻译：通过在一个有源区中形成基本上连续且均匀的半导体合金，同时在第二有源区中图案化半导体合金，以便在其中心部分提供基极半导体材料，可以诱发不同类型的应变，可以使用基底半导体材料的相应的覆盖层，用于形成栅极电介质的完善的工艺技术。在一些说明性实施例中，提供了基本上自对准的工艺，其中栅电极可以基于层形成，其也已经用于限定一个有源区的基极半导体材料的中心部分。因此，通过使用单个半导体合金，可以单独提高不同导电类型的晶体管的性能。

4. 发明授权

US07893503B2 Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain 有权
标题翻译：半导体器件包括具有嵌入的Si / Ge材料的NMOS和PMOS晶体管，用于产生拉伸和压缩应变
公开(公告)号：US07893503B2
公开(公告)日：2011-02-22
申请号：US12754819
申请日：2010-04-06
申请人： Sven Beyer , Manfred Horstmann , Patrick Press , Wolfgang Buchholtz
发明人： Sven Beyer , Manfred Horstmann , Patrick Press , Wolfgang Buchholtz
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823807 , H01L29/165 , H01L29/66621 , H01L29/66651 , H01L29/7833 , H01L29/7848 , H01L29/7849
摘要： By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.
摘要翻译：通过在一个有源区中形成基本上连续且均匀的半导体合金，同时在第二有源区中图案化半导体合金，以便在其中心部分提供基极半导体材料，可以诱发不同类型的应变，可以使用基底半导体材料的相应的覆盖层，用于形成栅极电介质的完善的工艺技术。在一些示例性实施例中，提供了基本上自对准的工艺，其中栅电极可以基于层形成，其也已经用于限定一个有源区的基极半导体材料的中心部分。因此，通过使用单个半导体合金，可以单独提高不同导电类型的晶体管的性能。

5. 发明授权

US07332384B2 Technique for forming a substrate having crystalline semiconductor regions of different characteristics 有权
标题翻译：用于形成具有不同特性的晶体半导体区域的衬底的技术
公开(公告)号：US07332384B2
公开(公告)日：2008-02-19
申请号：US11099761
申请日：2005-04-06
申请人： Wolfgang Buchholtz , Stephan Kruegel
发明人： Wolfgang Buchholtz , Stephan Kruegel
IPC分类号： H01L21/84
CPC分类号： H01L21/823878 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/7846
摘要： Different types of crystalline semiconductor regions are provided on a single substrate by forming a dielectric region within a first crystalline semiconductor region. Thereafter, a second crystalline region is positioned above the dielectric region by wafer bond techniques. In preferred embodiments, isolation structures may be formed in the first crystalline region along with the dielectric region. In particular, crystalline semiconductor regions of different crystallographic orientations may be formed, wherein a high degree of flexibility and compatibility with currently used CMOS processes is maintained.
摘要翻译：通过在第一晶体半导体区域内形成电介质区域，在单个衬底上提供不同类型的晶体半导体区域。此后，通过晶片键合技术将第二晶体区域位于电介质区域的上方。在优选实施例中，隔离结构可以与电介质区域一起形成在第一晶体区域中。特别地，可以形成不同晶体取向的晶体半导体区域，其中保持了高度的灵活性和与当前使用的CMOS工艺的兼容性。

6. 发明授权

US08039335B2 Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain 有权
公开(公告)号：US08039335B2
公开(公告)日：2011-10-18
申请号：US13005676
申请日：2011-01-13
申请人： Sven Beyer , Manfred Horstmann , Patrick Press , Wolfgang Buchholtz
发明人： Sven Beyer , Manfred Horstmann , Patrick Press , Wolfgang Buchholtz
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/165 , H01L29/66621 , H01L29/66651 , H01L29/7833 , H01L29/7848 , H01L29/7849
摘要： By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.

7. 发明授权

US07741167B2 Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain 有权
标题翻译：半导体器件包括具有嵌入的Si / Ge材料的NMOS和PMOS晶体管，用于产生拉伸和压缩应变
公开(公告)号：US07741167B2
公开(公告)日：2010-06-22
申请号：US11748902
申请日：2007-05-15
申请人： Sven Beyer , Manfred Horstmann , Patrick Press , Wolfgang Buchholtz
发明人： Sven Beyer , Manfred Horstmann , Patrick Press , Wolfgang Buchholtz
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/165 , H01L29/66621 , H01L29/66651 , H01L29/7833 , H01L29/7848 , H01L29/7849
摘要： By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.
摘要翻译：通过在一个有源区中形成基本上连续且均匀的半导体合金，同时在第二有源区中图案化半导体合金，以便在其中心部分提供基极半导体材料，可以诱发不同类型的应变，可以使用基底半导体材料的相应的覆盖层，用于形成栅极电介质的完善的工艺技术。在一些说明性实施例中，提供了基本上自对准的工艺，其中栅电极可以基于层形成，其也已经用于限定一个有源区的基极半导体材料的中心部分。因此，通过使用单个半导体合金，可以单独提高不同导电类型的晶体管的性能。

8. 发明授权

US07316975B2 Method of forming sidewall spacers 有权
标题翻译：形成侧墙的方法
公开(公告)号：US07316975B2
公开(公告)日：2008-01-08
申请号：US11177216
申请日：2005-07-08
申请人： Markus Lenski , Wolfgang Buchholtz , Andy Wei , Michael Raab
发明人： Markus Lenski , Wolfgang Buchholtz , Andy Wei , Michael Raab
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/823468
摘要： A substrate comprising a first transistor element and a second transistor element is provided. A layer of a material is deposited over the first transistor element and the second transistor element. A portion of the layer of material is modified, which may be done, e.g., by irradiating the portion with ions or performing an isotropic etching process to reduce its thickness. An etching process adapted to remove the modified portion of the layer of material more quickly than an unmodified portion of the layer located over the second transistor element is performed.
摘要翻译：提供了包括第一晶体管元件和第二晶体管元件的衬底。一层材料沉积在第一晶体管元件和第二晶体管元件上。材料层的一部分被修饰，其可以例如通过用离子照射部分或执行各向同性蚀刻工艺来实现，以减小其厚度。执行适于比位于第二晶体管元件上方的层的未修改部分更快地去除材料层的修饰部分的蚀刻工艺。

9. 发明申请

US20060094193A1 Semiconductor device including semiconductor regions having differently strained channel regions and a method of manufacturing the same 审中-公开
标题翻译：包括具有不同应变通道区域的半导体区域的半导体器件及其制造方法
公开(公告)号：US20060094193A1
公开(公告)日：2006-05-04
申请号：US11145697
申请日：2005-06-06
申请人： Manfred Horstmann , Ekkehard Pruefer , Wolfgang Buchholtz
发明人： Manfred Horstmann , Ekkehard Pruefer , Wolfgang Buchholtz
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/26506 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/66583 , H01L29/7833 , H01L29/7843
摘要： By locally modifying the intrinsic stress of a dielectric layer laterally enclosing gate electrode structures of a transistor configuration formed in accordance with in-laid gate techniques, the charge carrier mobility of different transistor elements may individually be adjusted. In particular, in in-laid gate structure transistor architecture, NMOS transistors and PMOS transistors may receive a tensile and a compressive stress, respectively.
摘要翻译：通过局部改变根据叠层栅极技术形成的晶体管配置的横向包围栅电极结构的电介质层的固有应力，可以单独地调节不同晶体管元件的电荷载流子迁移率。特别地，在嵌入式栅结构晶体管架构中，NMOS晶体管和PMOS晶体管可以分别接收拉伸和压缩应力。

10. 发明申请

US20050023611A1 Field effect transistor having a doped gate electrode with reduced gate depletion and method of forming the transistor 有权
标题翻译：场效应晶体管具有栅极耗尽减少的掺杂栅极和形成晶体管的方法
公开(公告)号：US20050023611A1
公开(公告)日：2005-02-03
申请号：US10790852
申请日：2004-03-02
申请人： Karsten Wieczorek , Thomas Feudel , Thorsten Kammler , Wolfgang Buchholtz
发明人： Karsten Wieczorek , Thomas Feudel , Thorsten Kammler , Wolfgang Buchholtz
IPC分类号： H01L21/336 , H01L29/49 , H01L29/786 , H01L21/00 , H01L27/01
CPC分类号： H01L29/66553 , H01L29/4908 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66772 , H01L29/78618 , H01L29/78621 , H01L29/78636
摘要： By forming an implantation mask prior to the definition of the drain and the source areas, an effective decoupling of the gate dopant concentration from that of the drain and source concentrations is achieved. Moreover, after removal of the implantation mask, the lateral dimension of the gate electrode may be defined by well-established sidewall spacer techniques, thereby providing a scaling advantage with respect to conventional approaches based on photolithography and anisotropic etching.
摘要翻译：通过在漏极和源极区域的定义之前形成注入掩模，实现了栅极掺杂剂浓度与漏极和源极浓度的有效去耦。此外，在移除注入掩模之后，栅极的横向尺寸可以通过公认的侧壁间隔物技术来限定，从而相对于基于光刻和各向异性蚀刻的常规方法提供缩放优点。

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