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    • 2. 发明授权
    • DRAM cell based on conductive nanochannel plate
    • 基于导电纳米通道板的DRAM单元
    • US08785271B2
    • 2014-07-22
    • US13017682
    • 2011-01-31
    • Dmytro ChumakovWolfgang BuchholtzPetra Hetzer
    • Dmytro ChumakovWolfgang BuchholtzPetra Hetzer
    • H01L21/8242
    • H01L27/1082B82Y10/00H01L27/10852H01L28/90
    • A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask.
    • 在导电体中的纳米通道中形成电容器。 实施例包括通过第一层间电介质(ILD)形成源极接触,在第一ILD上形成导电体,在导电体上形成第二ILD,通过第二ILD,导电体和第一ILD形成漏极和栅极接触 在导电体中形成纳米通道,在通道中形成绝缘层,并使通道金属化。 一个实施方案包括通过在第二ILD上形成掩模形成纳米通道,该掩模具有50纳米(nm)至100nm的间距的特征,通过掩模蚀刻第二ILD,通过掩模将导电体蚀刻到 深度为导电体的厚度的80%至90%,并且去除掩模。
    • 7. 发明申请
    • DRAM CELL BASED ON CONDUCTIVE NANOCHANNEL PLATE
    • 基于导电纳米通道板的DRAM单元
    • US20120193807A1
    • 2012-08-02
    • US13017682
    • 2011-01-31
    • Dmytro ChumakovWolfgang BuchholtzPetra Hetzer
    • Dmytro ChumakovWolfgang BuchholtzPetra Hetzer
    • H01L23/48H01L21/768
    • H01L27/1082B82Y10/00H01L27/10852H01L28/90
    • A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask.
    • 在导电体中的纳米通道中形成电容器。 实施例包括通过第一层间电介质(ILD)形成源极接触,在第一ILD上形成导电体,在导电体上形成第二ILD,通过第二ILD,导电体和第一ILD形成漏极和栅极接触 在导电体中形成纳米通道,在通道中形成绝缘层,并使通道金属化。 一个实施方案包括通过在第二ILD上形成掩模形成纳米通道,该掩模具有50纳米(nm)至100nm的间距的特征,通过掩模蚀刻第二ILD,通过掩模将导电体蚀刻到 深度为导电体的厚度的80%至90%,并且去除掩模。