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1. 发明授权

US08925396B2 Method and system for particles analysis in microstructure devices by isolating particles 有权
标题翻译：通过分离颗粒在微结构器件中进行颗粒分析的方法和系统
公开(公告)号：US08925396B2
公开(公告)日：2015-01-06
申请号：US12725688
申请日：2010-03-17
申请人： Petra Hetzer , Matthias Schaller , Dmytro Chumakov
发明人： Petra Hetzer , Matthias Schaller , Dmytro Chumakov
IPC分类号： G01N1/04 , G01N1/02 , G01N15/00 , H01L21/66
CPC分类号： G01N1/02 , G01N2001/028 , G01N2015/0038 , H01L22/12
摘要： During the fabrication of microstructure devices, such as integrated circuits, particles may be analyzed by displacing or removing the particles from the device surface and subsequently performing an analysis process. Consequently, a well-defined measurement environment may be established after removal of the particles, which may be accomplished on the basis of nanoprobes and the like. Hence, even critical surface areas may be monitored with respect to contamination and the like on the basis of well-established analysis techniques.
摘要翻译：在诸如集成电路的微结构器件的制造期间，可以通过从器件表面移位或移除颗粒并随后执行分析过程来分析颗粒。因此，可以在去除颗粒之后建立明确的测量环境，这可以基于纳米探针等来实现。因此，即使关键的表面积也可以基于已知的分析技术来监测污染等。

2. 发明授权

US08785271B2 DRAM cell based on conductive nanochannel plate 有权
标题翻译：基于导电纳米通道板的DRAM单元
公开(公告)号：US08785271B2
公开(公告)日：2014-07-22
申请号：US13017682
申请日：2011-01-31
申请人： Dmytro Chumakov , Wolfgang Buchholtz , Petra Hetzer
发明人： Dmytro Chumakov , Wolfgang Buchholtz , Petra Hetzer
IPC分类号： H01L21/8242
CPC分类号： H01L27/1082 , B82Y10/00 , H01L27/10852 , H01L28/90
摘要： A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask.
摘要翻译：在导电体中的纳米通道中形成电容器。实施例包括通过第一层间电介质（ILD）形成源极接触，在第一ILD上形成导电体，在导电体上形成第二ILD，通过第二ILD，导电体和第一ILD形成漏极和栅极接触在导电体中形成纳米通道，在通道中形成绝缘层，并使通道金属化。一个实施方案包括通过在第二ILD上形成掩模形成纳米通道，该掩模具有50纳米（nm）至100nm的间距的特征，通过掩模蚀刻第二ILD，通过掩模将导电体蚀刻到深度为导电体的厚度的80％至90％，并且去除掩模。

3. 发明授权

US08435885B2 Method and system for extracting samples after patterning of microstructure devices 有权
标题翻译：微结构器件图案化后提取样品的方法和系统
公开(公告)号：US08435885B2
公开(公告)日：2013-05-07
申请号：US13180143
申请日：2011-07-11
申请人： Dmytro Chumakov , Petra Hetzer , Matthias Schaller
发明人： Dmytro Chumakov , Petra Hetzer , Matthias Schaller
IPC分类号： H01L21/4763
CPC分类号： G01N1/04 , G01N2001/2833 , H01L21/02096
摘要： Analysis of chemical and physical characteristics of polymer species and etch residues caused in critical plasma-assisted etch processes for patterning material layers in semiconductor devices may be accomplished by removing at least a portion of these species on the basis of a probing material layer, which may be lifted-off from the patterned surface. The probing material layer may substantially suppress a chemical modification of the species of interest and may thus allow the examination of the initial status of these species.
摘要翻译：可以通过基于探测材料层去除这些物质的至少一部分来实现在半导体器件中的图形材料层的关键等离子体辅助蚀刻工艺中引起的聚合物种类和蚀刻残留物的化学和物理特性的分析，从图案的表面上脱下来。探测材料层可以基本上抑制感兴趣物种的化学修饰，并且因此可以允许检查这些物种的初始状态。

4. 发明申请

US20100242631A1 METHOD AND SYSTEM FOR PARTICLES ANALYSIS IN MICROSTRUCTURE DEVICES BY ISOLATING PARTICLES 有权
标题翻译：通过分离颗粒在微结构装置中分析颗粒的方法和系统
公开(公告)号：US20100242631A1
公开(公告)日：2010-09-30
申请号：US12725688
申请日：2010-03-17
申请人： Petra Hetzer , Matthias Schaller , Dmytro Chumakov
发明人： Petra Hetzer , Matthias Schaller , Dmytro Chumakov
IPC分类号： G01N1/04 , G01J3/44 , B01D59/44 , G01J5/02 , G01N23/225
CPC分类号： G01N1/02 , G01N2001/028 , G01N2015/0038 , H01L22/12
摘要： During the fabrication of microstructure devices, such as integrated circuits, particles may be analyzed by displacing or removing the particles from the device surface and subsequently performing an analysis process. Consequently, a well-defined measurement environment may be established after removal of the particles, which may be accomplished on the basis of nanoprobes and the like. Hence, even critical surface areas may be monitored with respect to contamination and the like on the basis of well-established analysis techniques.
摘要翻译：在诸如集成电路的微结构器件的制造期间，可以通过从器件表面移位或移除颗粒并随后执行分析过程来分析颗粒。因此，可以在去除颗粒之后建立明确的测量环境，这可以基于纳米探针等来实现。因此，即使关键的表面积也可以基于已知的分析技术来监测污染等。

5. 发明申请

US20100248498A1 MATERIAL STRIPPING IN SEMICONDUCTOR DEVICES BY EVAPORATION 审中-公开
标题翻译：通过蒸发在半导体器件中的材料剥离
公开(公告)号：US20100248498A1
公开(公告)日：2010-09-30
申请号：US12750042
申请日：2010-03-30
申请人： Petra Hetzer , Matthias Schaller , Daniel Fischer
发明人： Petra Hetzer , Matthias Schaller , Daniel Fischer
IPC分类号： H01L21/263 , B23K26/36
CPC分类号： H01L21/268 , H01L21/31127 , H01L21/31138 , H01L21/67115 , H01L29/6659
摘要： A sacrificial material, such as resist material, polymer material, organic residues and the like, may be efficiently removed from a surface of a semiconductor device by evaporating the material under consideration, which may, for instance, be accomplished by energy deposition. For example, a laser beam may be scanned across the surface to be treated so as to evaporate the sacrificial material, such as resist material, while significantly reducing any negative effects on other materials such as dielectrics, metals, semiconductive materials and the like. Moreover, by selecting an appropriate scan regime, a locally selective removal of material may be accomplished in a highly efficient manner.
摘要翻译：通过蒸发考虑的材料，可以有效地从半导体器件的表面去除牺牲材料，例如抗蚀剂材料，聚合物材料，有机残余物等，其可以例如通过能量沉积来实现。例如，激光束可以跨越要处理的表面进行扫描，以便蒸发诸如抗蚀剂材料的牺牲材料，同时显着地减少对诸如电介质，金属，半导体材料等的其它材料的任何负面影响。此外，通过选择适当的扫描方式，可以以高效的方式实现局部选择性去除材料。

6. 发明申请

US20060223311A1 Technique for forming interconnect structures with reduced electro and stress migration and/or resistivity 审中-公开
标题翻译：用于形成具有降低的电和应力迁移和/或电阻率的互连结构的技术
公开(公告)号：US20060223311A1
公开(公告)日：2006-10-05
申请号：US11264408
申请日：2005-11-01
申请人： Wolfgang Buchholtz , Petra Hetzer , Elvira Buchholtz
发明人： Wolfgang Buchholtz , Petra Hetzer , Elvira Buchholtz
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76828 , H01L21/76864 , H01L21/76873 , H01L21/76877
摘要： By improving the purity of metal lines and the crystalline structure, the overall performance of metal lines, especially of highly scaled copper-based semiconductor devices may be enhanced. The modification of the crystalline structure of the metal lines may be performed by a heat treatment generating locally restricted heating zones, which are scanned along the length direction of the metal lines.
摘要翻译：通过提高金属线的纯度和晶体结构，可以提高金属线，特别是高规模铜基半导体器件的整体性能。金属线的晶体结构的修改可以通过产生局部限制的加热区域的热处理来进行，这些区域沿金属线的长度方向被扫描。

7. 发明申请

US20120193807A1 DRAM CELL BASED ON CONDUCTIVE NANOCHANNEL PLATE 有权
标题翻译：基于导电纳米通道板的DRAM单元
公开(公告)号：US20120193807A1
公开(公告)日：2012-08-02
申请号：US13017682
申请日：2011-01-31
申请人： Dmytro Chumakov , Wolfgang Buchholtz , Petra Hetzer
发明人： Dmytro Chumakov , Wolfgang Buchholtz , Petra Hetzer
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L27/1082 , B82Y10/00 , H01L27/10852 , H01L28/90
摘要： A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask.
摘要翻译：在导电体中的纳米通道中形成电容器。实施例包括通过第一层间电介质（ILD）形成源极接触，在第一ILD上形成导电体，在导电体上形成第二ILD，通过第二ILD，导电体和第一ILD形成漏极和栅极接触在导电体中形成纳米通道，在通道中形成绝缘层，并使通道金属化。一个实施方案包括通过在第二ILD上形成掩模形成纳米通道，该掩模具有50纳米（nm）至100nm的间距的特征，通过掩模蚀刻第二ILD，通过掩模将导电体蚀刻到深度为导电体的厚度的80％至90％，并且去除掩模。

8. 发明申请

US20120052601A1 Method and System for Extracting Samples After Patterning of Microstructure Devices 有权
标题翻译：微结构器件图案化后提取样品的方法和系统
公开(公告)号：US20120052601A1
公开(公告)日：2012-03-01
申请号：US13180143
申请日：2011-07-11
申请人： Dmytro Chumakov , Petra Hetzer , Matthias Schaller
发明人： Dmytro Chumakov , Petra Hetzer , Matthias Schaller
IPC分类号： H01L21/66 , G01J5/02 , G01J3/44 , G01N23/00
CPC分类号： G01N1/04 , G01N2001/2833 , H01L21/02096
摘要： Analysis of chemical and physical characteristics of polymer species and etch residues caused in critical plasma-assisted etch processes for patterning material layers in semiconductor devices may be accomplished by removing at least a portion of these species on the basis of a probing material layer, which may be lifted-off from the patterned surface. The probing material layer may substantially suppress a chemical modification of the species of interest and may thus allow the examination of the initial status of these species.
摘要翻译：可以通过基于探测材料层去除这些物质的至少一部分来实现在半导体器件中图案化材料层的关键等离子体辅助蚀刻工艺中引起的聚合物种类和蚀刻残留物的化学和物理特性的分析，从图案的表面上脱下来。探测材料层可以基本上抑制感兴趣物种的化学修饰，并且因此可以允许检查这些物种的初始状态。

9. 发明授权

US07375031B2 Technique for forming interconnect structures with reduced electro and stress migration and/or resistivity 失效
标题翻译：用于形成具有降低的电和应力迁移和/或电阻率的互连结构的技术
公开(公告)号：US07375031B2
公开(公告)日：2008-05-20
申请号：US11292537
申请日：2005-12-02
申请人： Axel Preusse , Markus Keil , Wolfgang Buchholtz , Petra Hetzer , Elvira Buchholtz
发明人： Axel Preusse , Markus Keil , Wolfgang Buchholtz , Petra Hetzer , Elvira Buchholtz
IPC分类号： H01L21/44
CPC分类号： H01L21/76886 , H01L21/76864 , H01L21/76873 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： By improving the purity of metal lines and the crystalline structure, the overall performance of metal lines, especially of highly scaled copper-based semiconductor devices, may be enhanced. The modification of the crystalline structure of the metal lines may be performed by a heat treatment generating locally restricted heating zones, which are scanned along the length direction of the metal lines, and/or a heat treatment comprising a heating step in a vacuum ambient followed by a heating step in a reducing ambient.
摘要翻译：通过提高金属线的纯度和晶体结构，可以提高金属线，特别是高规模铜基半导体器件的整体性能。金属线的晶体结构的修改可以通过热处理来实现，所述热处理产生沿金属线的长度方向扫描的局部限制的加热区，和/或包括在真空环境中的加热步骤的热处理，随后通过在还原环境中的加热步骤。

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