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1. 发明授权

US08760593B2 Thin film transistor and method for manufacturing thereof 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US08760593B2
公开(公告)日：2014-06-24
申请号：US12221615
申请日：2008-08-05
申请人： Po-Lin Chen , Kuo-Yuan Tu , Wen-Ching Tsai , Chun-Nan Lin , Shu-Feng Wu
发明人： Po-Lin Chen , Kuo-Yuan Tu , Wen-Ching Tsai , Chun-Nan Lin , Shu-Feng Wu
IPC分类号： G02F1/136 , H01L29/04 , H01L21/00
CPC分类号： H01L29/458 , H01L27/124
摘要： A thin-film transistor (TFT) includes a gate electrode, a gate dielectric layer, a semiconductor layer, source/drain electrodes, a passivation layer and a protection layer. The gate electrode is disposed on a substrate. The gate dielectric layer covers the gate electrode and the substrate. The semiconductor layer is disposed on the gate dielectric layer and above the gate electrode. The semiconductor layer has a channel region disposed above the gate electrode and source/drain regions disposed at both sides of the channel region. The source/drain electrodes are disposed on the source/drain regions of the semiconductor layer and each has a barrier layer disposed on the source/drain regions of the semiconductor layer and a conductive layer disposed on the barrier layer. The passivation layer is disposed over the surface of the source/drain electrodes. The protection layer is disposed over the substrate, the passivation layer, and the channel region of the semiconductor layer.
摘要翻译：薄膜晶体管（TFT）包括栅电极，栅极电介质层，半导体层，源极/漏极，钝化层和保护层。栅电极设置在基板上。栅介质层覆盖栅电极和衬底。半导体层设置在栅极电介质层上并在栅电极上方。半导体层具有设置在沟道区两侧的栅电极和源极/漏极区上方的沟道区。源极/漏极设置在半导体层的源极/漏极区域上，并且每个具有设置在半导体层的源极/漏极区域上的势垒层和设置在阻挡层上的导电层。钝化层设置在源/漏电极的表面上。保护层设置在衬底，钝化层和半导体层的沟道区之上。

2. 发明授权

US08395149B2 Semiconductor device structure and method for manufacturing the same 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US08395149B2
公开(公告)日：2013-03-12
申请号：US12776484
申请日：2010-05-10
申请人： Yih-Chyun Kao , Chun-Nan Lin , Li-Kai Chen , Wen-Ching Tsai
发明人： Yih-Chyun Kao , Chun-Nan Lin , Li-Kai Chen , Wen-Ching Tsai
IPC分类号： H01L29/786 , H01L29/12
CPC分类号： H01L29/7869
摘要： A semiconductor device structure on a substrate and a manufacture method thereof is provided. The semiconductor device structure includes an oxide semiconductor transistor and a passivation layer containing free hydrogen. The semiconductor device structure is formed by following steps. A gate electrode is formed on the substrate. A gate dielectric layer covers the gate electrode. A source electrode is formed on the gate dielectric layer. A drain electrode is formed on the gate dielectric layer and separated from the source electrode and thereby forming a channel distance. An oxide semiconductor layer is formed on the gate dielectric layer, the source electrode and the drain electrode and between the source electrode and the drain electrode. The oxide semiconductor layer is further electrically connected with the source electrode and the drain electrode. A passivation layer covers the oxide semiconductor layer, the source electrode and the drain electrode. The passivation layer has a groove formed therein, and the groove surrounds the oxide semiconductor layer.
摘要翻译：提供了一种基板上的半导体器件结构及其制造方法。半导体器件结构包括氧化物半导体晶体管和含有游离氢的钝化层。半导体器件结构通过以下步骤形成。在基板上形成栅电极。栅介质层覆盖栅电极。源极电极形成在栅极电介质层上。在栅极电介质层上形成漏电极，与源电极分离，形成通道距离。在栅极电介质层，源电极和漏电极以及源电极和漏电极之间形成氧化物半导体层。氧化物半导体层进一步与源电极和漏电极电连接。钝化层覆盖氧化物半导体层，源电极和漏电极。钝化层在其中形成有凹槽，并且沟槽围绕氧化物半导体层。

3. 发明申请

US20120261755A1 PIXEL STRUCTURE, DISPLAY PANEL, ELECTRO-OPTICAL APPARATUS, AND METHOD THEREOF 审中-公开
标题翻译：像素结构，显示面板，电光设备及其方法
公开(公告)号：US20120261755A1
公开(公告)日：2012-10-18
申请号：US13477077
申请日：2012-05-22
申请人： Po-Lin Chen , Chun-Nan Lin , Shu-Feng Wu , Wen-Ching Tsai
发明人： Po-Lin Chen , Chun-Nan Lin , Shu-Feng Wu , Wen-Ching Tsai
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/458 , H01L27/124 , H01L27/1255
摘要： A pixel structure disposed on a substrate including a thin film transistor (TFT), a passivation layer, and a pixel electrode is provided. The TFT includes a gate, a dielectric layer, a channel layer, and a source/drain sequentially disposed on the substrate. The source/drain is disposed on a portion of the channel layer and has a semiconductor layer, a barrier layer and a metal layer. The barrier layer is disposed on a portion of the semiconductor layer. The metal layer is disposed on the barrier layer. The barrier layer is in contact with the semiconductor layer and the metal layer. Both of the metal layer and the barrier layer are positioned within a projection area of the semiconductor layer. The passivation layer covers the TFT and the dielectric layer and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.
摘要翻译：设置在包括薄膜晶体管（TFT），钝化层和像素电极的基板上的像素结构。 TFT包括顺序地设置在基板上的栅极，电介质层，沟道层和源极/漏极。源极/漏极设置在沟道层的一部分上并具有半导体层，势垒层和金属层。阻挡层设置在半导体层的一部分上。金属层设置在阻挡层上。阻挡层与半导体层和金属层接触。金属层和阻挡层都位于半导体层的投影区域内。钝化层覆盖TFT和电介质层，并且具有暴露源极/漏极的第一开口。像素电极通过第一开口与TFT电连接。

4. 发明授权

US08232591B2 Illuminating efficiency-increasable and light-erasable memory 有权
标题翻译：照明效率可提高和轻型可擦除记忆
公开(公告)号：US08232591B2
公开(公告)日：2012-07-31
申请号：US12431130
申请日：2009-04-28
申请人： Hung-Lin Shih , Wen-Ching Tsai , Yu-Hua Huang
发明人： Hung-Lin Shih , Wen-Ching Tsai , Yu-Hua Huang
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L23/5258 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： An illuminating efficiency-increasable and light-erasable memory including a substrate, a memory device, many dielectric layers, and many cap layers is provided. The substrate includes a memory region. The memory device includes a select gate and a floating gate, and the select gate and the floating gate are disposed adjacently on the substrate in the memory region. The dielectric layers are disposed on the substrate and cover the memory device. The dielectric layers have an opening located above the floating gate. Each of the cap layers is disposed on each of the dielectric layers, respectively.
摘要翻译：提供了包括基板，存储器件，许多电介质层和许多盖层的照明效率可增加和可光擦除的存储器。衬底包括存储区域。存储器件包括选择栅极和浮置栅极，并且选择栅极和浮置栅极相邻地设置在存储器区域中的衬底上。电介质层设置在基板上并覆盖存储器件。电介质层具有位于浮动栅极上方的开口。每个盖层分别设置在每个电介质层上。

5. 发明授权

US07732886B2 Pin photodiode structure 有权
标题翻译：引脚光电二极管结构
公开(公告)号：US07732886B2
公开(公告)日：2010-06-08
申请号：US12173807
申请日：2008-07-15
申请人： Hung-Lin Shih , Tsan-Chi Chu , Wen-Shiang Liao , Wen-Ching Tsai
发明人： Hung-Lin Shih , Tsan-Chi Chu , Wen-Shiang Liao , Wen-Ching Tsai
IPC分类号： H01L29/06
CPC分类号： H01L31/1055 , H01L27/1203 , H01L31/028 , H01L31/105 , H01L31/1808 , Y02E10/547
摘要： A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.
摘要翻译： PIN光电二极管结构包括衬底，设置在衬底中的P掺杂区域，设置在衬底中的N掺杂区域和设置在衬底中并且在P掺杂区域和N掺杂区域之间的第一半导体材料。

6. 发明申请

US20090206384A1 ILLUMINATING EFFICIENCY-INCREASABLE AND LIGHT-ERASABLE MEMORY 有权
标题翻译：提高效率和可擦除光记忆
公开(公告)号：US20090206384A1
公开(公告)日：2009-08-20
申请号：US12431130
申请日：2009-04-28
申请人： Hung-Lin Shih , Wen-Ching Tsai , Yu-Hua Huang
发明人： Hung-Lin Shih , Wen-Ching Tsai , Yu-Hua Huang
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L23/5258 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： An illuminating efficiency-increasable and light-erasable memory including a substrate, a memory device, many dielectric layers, and many cap layers is provided. The substrate includes a memory region. The memory device includes a select gate and a floating gate, and the select gate and the floating gate are disposed adjacently on the substrate in the memory region. The dielectric layers are disposed on the substrate and cover the memory device. The dielectric layers have an opening located above the floating gate. Each of the cap layers is disposed on each of the dielectric layers, respectively.
摘要翻译：提供了包括基板，存储器件，许多电介质层和许多盖层的照明效率可增加和可光擦除的存储器。衬底包括存储区域。存储器件包括选择栅极和浮置栅极，并且选择栅极和浮置栅极相邻地设置在存储器区域中的衬底上。电介质层设置在基板上并覆盖存储器件。电介质层具有位于浮动栅极上方的开口。每个盖层分别设置在每个电介质层上。

7. 发明授权

US07528466B2 Copper gate electrode of liquid crystal display device and method of fabricating the same 有权
标题翻译：液晶显示装置的铜栅电极及其制造方法
公开(公告)号：US07528466B2
公开(公告)日：2009-05-05
申请号：US11178436
申请日：2005-07-12
申请人： Yu-Wei Liu , Wen-Ching Tsai , Kuo-Yu Huang , Hui-Fen Lin
发明人： Yu-Wei Liu , Wen-Ching Tsai , Kuo-Yu Huang , Hui-Fen Lin
IPC分类号： H01L21/20
CPC分类号： H01L29/4908
摘要： A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M1M2R wherein M1 is cobalt (Co) or molybdenum (Mo), M2 is tungsten (W), molybdenum (Mo), rhenium (Re) or vanadium (V), and R is boron (B) or phosphorus (P).
摘要翻译：施加在薄膜晶体管液晶显示器（LCD）装置中的铜栅电极至少包括形成在玻璃基板上的图案化铜层和形成在图案化铜层上的阻挡层。阻挡层包括氮和磷中的至少一种，或包含形式为M1M2R的合金，其中M1是钴（Co）或钼（Mo），M2是钨（W），钼（Mo），铼（Re）或钒（V），R为硼（B）或磷（P）。

8. 发明申请

US20090057668A1 Display Element and Method of Manufacturing the Same 有权
标题翻译：显示元件及其制造方法
公开(公告)号：US20090057668A1
公开(公告)日：2009-03-05
申请号：US12115855
申请日：2008-05-06
申请人： Po-Lin Chen , Wen-Ching Tsai , Chun-Nan Lin , Kuo-Yuan Tu
发明人： Po-Lin Chen , Wen-Ching Tsai , Chun-Nan Lin , Kuo-Yuan Tu
IPC分类号： H01L29/786 , H01L21/8234
CPC分类号： H01L29/458 , H01L27/124 , H01L29/41733
摘要： A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.
摘要翻译：提供了一种显示元件及其制造方法。该方法包括以下步骤：在衬底上形成具有栅极的第一图案化导电层和其上的电介质层; 在所述电介质层上形成图案化的半导体层，其中所述图案化半导体层具有沟道区，源极和漏极，并且其中所述源极和漏极位于所述沟道区的相对侧上; 选择性地沉积仅包裹图案化半导体层的阻挡层; 在阻挡层上和源极和漏极之上形成第二图案化导电层。在通过该方法制造的显示元件中，阻挡层仅包裹图案化的半导体层。

9. 发明申请

US20060138659A1 Copper gate electrode of liquid crystal display device and method of fabricating the same 有权
标题翻译：液晶显示装置的铜栅电极及其制造方法
公开(公告)号：US20060138659A1
公开(公告)日：2006-06-29
申请号：US11178436
申请日：2005-07-12
申请人： Yu-Wei Liu , Wen-Ching Tsai , Kuo-Yu Huang , Hui-Fen Lin
发明人： Yu-Wei Liu , Wen-Ching Tsai , Kuo-Yu Huang , Hui-Fen Lin
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L29/4908
摘要： A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M1M2R wherein M1 is cobalt (Co) or molybdenum (Mo), M2 is tungsten (W), molybdenum (Mo), rhenium (Re) or vanadium (V), and R is boron (B) or phosphorus (P).
摘要翻译：施加在薄膜晶体管液晶显示器（LCD）装置中的铜栅电极至少包括形成在玻璃基板上的图案化铜层和形成在图案化铜层上的阻挡层。阻挡层包括氮和磷中的至少一种，或者包含配位为M 1 M 2 R 2的合金，其中M 1是钴（ Co）或钼（Mo），M 2是钨（W），钼（Mo），铼（Re）或钒（V），R是硼（B）或磷（P）。

10. 发明授权

US08212256B2 Pixel structure, display panel, eletro-optical apparatus, and method thererof 有权
标题翻译：像素结构，显示面板，电光设备及其方法
公开(公告)号：US08212256B2
公开(公告)日：2012-07-03
申请号：US12060873
申请日：2008-04-02
申请人： Po-Lin Chen , Chun-Nan Lin , Shu-Feng Wu , Wen-Ching Tsai
发明人： Po-Lin Chen , Chun-Nan Lin , Shu-Feng Wu , Wen-Ching Tsai
IPC分类号： H01L29/04
CPC分类号： H01L29/458 , H01L27/124 , H01L27/1255
摘要： A pixel structure disposed on a substrate including a thin film transistor (TFT), a bottom capacitor electrode, a dielectric layer, an upper capacitor electrode, a passivation layer, and a pixel electrode is provided. The TFT having a source/drain and the bottom capacitor electrode are disposed on the substrate. The dielectric layer is disposed on the bottom capacitor electrode. The upper capacitor electrode has a semiconductor layer, a barrier layer, and a metal layer. The semiconductor layer is disposed on the dielectric layer above the bottom capacitor electrode. The barrier layer is disposed on the semiconductor layer. The metal layer whose material includes copper, a copper alloy, or a combination thereof is disposed on the barrier layer. The passivation layer covers the TFT and the upper capacitor electrode and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.
摘要翻译：提供了一种设置在包括薄膜晶体管（TFT），底部电容器电极，电介质层，上部电容器电极，钝化层和像素电极的基板上的像素结构。具有源极/漏极和底部电容器电极的TFT设置在衬底上。电介质层设置在底部电容器电极上。上部电容器电极具有半导体层，阻挡层和金属层。半导体层设置在底部电容器电极上方的电介质层上。阻挡层设置在半导体层上。其材料包括铜，铜合金或其组合的金属层设置在阻挡层上。钝化层覆盖TFT和上电容器电极，并且具有暴露源极/漏极的第一开口。像素电极通过第一开口与TFT电连接。

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