专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07732886B2 Pin photodiode structure 有权
标题翻译：引脚光电二极管结构
公开(公告)号：US07732886B2
公开(公告)日：2010-06-08
申请号：US12173807
申请日：2008-07-15
申请人： Hung-Lin Shih , Tsan-Chi Chu , Wen-Shiang Liao , Wen-Ching Tsai
发明人： Hung-Lin Shih , Tsan-Chi Chu , Wen-Shiang Liao , Wen-Ching Tsai
IPC分类号： H01L29/06
CPC分类号： H01L31/1055 , H01L27/1203 , H01L31/028 , H01L31/105 , H01L31/1808 , Y02E10/547
摘要： A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.
摘要翻译： PIN光电二极管结构包括衬底，设置在衬底中的P掺杂区域，设置在衬底中的N掺杂区域和设置在衬底中并且在P掺杂区域和N掺杂区域之间的第一半导体材料。

2. 发明申请

US20100012974A1 PIN PHOTODIODE STRUCTURE AND METHOD FOR MAKING THE SAME 有权
标题翻译： PIN光电结构及其制造方法
公开(公告)号：US20100012974A1
公开(公告)日：2010-01-21
申请号：US12173807
申请日：2008-07-15
申请人： Hung-Lin Shih , Tsan-Chi Chu , Wen-Shiang Liao , Wen-Ching Tsai
发明人： Hung-Lin Shih , Tsan-Chi Chu , Wen-Shiang Liao , Wen-Ching Tsai
IPC分类号： H01L31/0336 , H01L31/105 , H01L31/18
CPC分类号： H01L31/1055 , H01L27/1203 , H01L31/028 , H01L31/105 , H01L31/1808 , Y02E10/547
摘要： A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.
摘要翻译： PIN光电二极管结构包括衬底，设置在衬底中的P掺杂区域，设置在衬底中的N掺杂区域和设置在衬底中并且在P掺杂区域和N掺杂区域之间的第一半导体材料。

3. 发明申请

US20090294903A1 ANTI-FUSSE STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：抗融合结构及其制造方法
公开(公告)号：US20090294903A1
公开(公告)日：2009-12-03
申请号：US12132111
申请日：2008-06-03
申请人： Hung-Lin Shih , Wen-Shiang Liao , Tsan-Chi Chu
发明人： Hung-Lin Shih , Wen-Shiang Liao , Tsan-Chi Chu
IPC分类号： H01L23/525 , H01L21/02
CPC分类号： H01L23/5252 , H01L27/0733 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure and a method of fabricating the same are described. The anti-fuse structure is disposed over a substrate having at least one device and a copper layer therein. The anti-fuse structure includes a bottom conductive layer, an insulating layer and a top conductive layer. The bottom conductive layer is disposed over and electrically connected with the copper layer. The insulating layer is conformally disposed over the bottom conductive layer covering a corner or a downward turning portion of the bottom conductive layer to form a turning portion of the insulating layer. The top conductive layer is conformally disposed over the insulting layer covering the turning portion of the insulating layer.
摘要翻译：描述了一种抗熔丝结构及其制造方法。反熔丝结构设置在其中具有至少一个器件和铜层的衬底上。反熔丝结构包括底部导电层，绝缘层和顶部导电层。底部导电层设置在铜层上并与铜层电连接。绝缘层保形地设置在覆盖底部导电层的拐角或向下转动部分的底部导电层上，以形成绝缘层的转动部分。顶部导电层保形地设置在覆盖绝缘层的转向部分的绝缘层上。

4. 发明授权

US08022503B2 Anti-fusse structure and method of fabricating the same 有权
标题翻译：反融体结构及其制造方法
公开(公告)号：US08022503B2
公开(公告)日：2011-09-20
申请号：US12132111
申请日：2008-06-03
申请人： Hung-Lin Shih , Wen-Shiang Liao , Tsan-Chi Chu
发明人： Hung-Lin Shih , Wen-Shiang Liao , Tsan-Chi Chu
IPC分类号： H01L23/525 , H01L21/02
CPC分类号： H01L23/5252 , H01L27/0733 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure and a method of fabricating the same are described. The anti-fuse structure is disposed over a substrate having at least one device and a copper layer therein. The anti-fuse structure includes a bottom conductive layer, an insulating layer and a top conductive layer. The bottom conductive layer is disposed over and electrically connected with the copper layer. The insulating layer is conformally disposed over the bottom conductive layer covering a corner or a downward turning portion of the bottom conductive layer to form a turning portion of the insulating layer. The top conductive layer is conformally disposed over the insulting layer covering the turning portion of the insulating layer.
摘要翻译：描述了一种抗熔丝结构及其制造方法。反熔丝结构设置在其中具有至少一个器件和铜层的衬底上。反熔丝结构包括底部导电层，绝缘层和顶部导电层。底部导电层设置在铜层上并与铜层电连接。绝缘层保形地设置在覆盖底部导电层的拐角或向下转动部分的底部导电层上，以形成绝缘层的转动部分。顶部导电层保形地设置在覆盖绝缘层的转向部分的绝缘层上。

5. 发明授权

US08536653B2 Metal oxide semiconductor transistor 有权
标题翻译：金属氧化物半导体晶体管
公开(公告)号：US08536653B2
公开(公告)日：2013-09-17
申请号：US12904166
申请日：2010-10-14
申请人： Hung-Lin Shih , Tsan-Chi Chu
发明人： Hung-Lin Shih , Tsan-Chi Chu
IPC分类号： H01L21/70
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A metal oxide semiconductor transistor includes a substrate including a first well, a second well, and an insulation between the first well and the second well, a first gate structure disposed on the first well, a second gate structure disposed on the second well, four first dopant regions disposed in the substrate at two sides of the first gate structure, and in the substrate at two sides of the second gate structure respectively, two second dopant regions disposed in the substrate at two sides of the first gate structure respectively, two first epitaxial layers disposed in the substrate at two sides of the first gate structure respectively and two first source/drain regions disposed in the substrate at two sides of the first gate structure respectively, wherein each of the first source/drain regions overlaps with one of the first epitaxial layers and one of the second dopant regions simultaneously.
摘要翻译：一种金属氧化物半导体晶体管包括：基板，包括第一阱，第二阱以及第一阱和第二阱之间的绝缘，设置在第一阱上的第一栅极结构，设置在第二阱上的第二栅极结构，分别在第一栅极结构的两侧设置在基板中的第一掺杂区域和分别在第二栅极结构的两侧的基板中，分别在第一栅极结构的两侧设置在基板中的两个第二掺杂区域，分别在第一栅极结构的两侧设置在基板中的外延层和分别在第一栅极结构的两侧设置在基板中的两个第一源极/漏极区域，其中每个第一源极/漏极区域与第一外延层和第二掺杂区之一同时。

6. 发明申请

US20090261401A1 NON-VOLATILE MEMORY CELL AND METHOD OF FABRICATING THE SAME 有权
标题翻译：非挥发性记忆体及其制备方法
公开(公告)号：US20090261401A1
公开(公告)日：2009-10-22
申请号：US12104452
申请日：2008-04-17
申请人： Hung-Lin Shih , Tsan-Chi Chu
发明人： Hung-Lin Shih , Tsan-Chi Chu
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7923 , H01L21/28282 , H01L29/66833
摘要： A non-volatile memory cell is described, including a semiconductor substrate, two separate charge trapping structures on the substrate, first spacers at least on the opposite sidewalls of the two charge trapping structures, a gate dielectric layer on the substrate between the two charge trapping structures, a gate on the two charge trapping structures and the gate dielectirc layer, and two doped regions in the substrate beside the gate.
摘要翻译：描述了非易失性存储器单元，包括半导体衬底，衬底上的两个单独的电荷俘获结构，至少在两个电荷俘获结构的相对侧壁上的第一间隔物，两个电荷俘获之间的衬底上的栅极介电层结构，两个电荷捕获结构上的栅极和栅极介电层，以及栅极旁边的衬底中的两个掺杂区域。

7. 发明申请

US20080085577A1 METHOD OF MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTOR 有权
标题翻译：制备补充金属氧化物半导体晶体管的方法
公开(公告)号：US20080085577A1
公开(公告)日：2008-04-10
申请号：US11538815
申请日：2006-10-05
申请人： Hung-Lin Shih , Tsan-Chi Chu
发明人： Hung-Lin Shih , Tsan-Chi Chu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method of manufacturing a CMOS is disclosed. A substrate has a first gate and a second gate. A dielectric layer and a patterned photo-resist layer are formed sequentially on the substrate. After an etching process, the dielectric layer without the photo-resist layer forms a spacer around the first gate, and the dielectric layer with the photo-resist layer forms a block layer on the second gate. The recesses are formed in the substrate of two lateral sides of the first gate. The epitaxial silicon layers are formed in the recesses.
摘要翻译：公开了制造CMOS的方法。衬底具有第一栅极和第二栅极。在基板上依次形成电介质层和图案化的光致抗蚀剂层。在蚀刻处理之后，没有光致抗蚀剂层的电介质层在第一栅极周围形成间隔物，并且具有光致抗蚀剂层的电介质层在第二栅极上形成阻挡层。凹槽形成在第一浇口的两个侧面的基底中。在凹槽中形成外延硅层。

8. 发明授权

US07998821B2 Method of manufacturing complementary metal oxide semiconductor transistor 有权
标题翻译：互补金属氧化物半导体晶体管的制造方法
公开(公告)号：US07998821B2
公开(公告)日：2011-08-16
申请号：US11538815
申请日：2006-10-05
申请人： Hung-Lin Shih , Tsan-Chi Chu
发明人： Hung-Lin Shih , Tsan-Chi Chu
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method of manufacturing a CMOS is disclosed. A substrate has a first gate and a second gate. A dielectric layer and a patterned photo-resist layer are formed sequentially on the substrate. After an etching process, the dielectric layer without the photo-resist layer forms a spacer around the first gate, and the dielectric layer with the photo-resist layer forms a block layer on the second gate. The recesses are formed in the substrate of two lateral sides of the first gate. The epitaxial silicon layers are formed in the recesses.
摘要翻译：公开了制造CMOS的方法。衬底具有第一栅极和第二栅极。在基板上依次形成电介质层和图案化的光致抗蚀剂层。在蚀刻处理之后，没有光致抗蚀剂层的电介质层在第一栅极周围形成间隔物，并且具有光致抗蚀剂层的电介质层在第二栅极上形成阻挡层。凹部形成在第一浇口的两个侧面的基板中。在凹槽中形成外延硅层。

9. 发明申请

US20110097866A1 NON-VOLATILE MEMORY CELL AND METHOD OF FABRICATING THE SAME 有权
标题翻译：非挥发性记忆体及其制备方法
公开(公告)号：US20110097866A1
公开(公告)日：2011-04-28
申请号：US12985322
申请日：2011-01-05
申请人： Hung-Lin Shih , Tsan-Chi Chu
发明人： Hung-Lin Shih , Tsan-Chi Chu
IPC分类号： H01L21/336
CPC分类号： H01L29/7923 , H01L21/28282 , H01L29/66833
摘要： A method of fabricating a non-volatile memory cell is disclosed. The method includes the steps of: forming two separate charge trapping structures on a semiconductor substrate; forming first spacers on sidewalls of the two charge trapping structures; forming a gate dielectric layer on the substrate; forming a gate on the two charge trapping structures and the gate dielectric layer between the two charge trapping structures; and forming two doped regions in the substrate besdie the gate.
摘要翻译：公开了一种制造非易失性存储单元的方法。该方法包括以下步骤：在半导体衬底上形成两个独立的电荷俘获结构; 在所述两个电荷俘获结构的侧壁上形成第一间隔物; 在所述基板上形成栅介电层; 在两个电荷俘获结构之间形成栅极，并在两个电荷俘获结构之间形成栅极电介质层; 以及在衬底中形成栅极的两个掺杂区域。

10. 发明授权

US08409945B2 Method of fabricating a charge trapping non-volatile memory cell 有权
标题翻译：制造电荷捕获非易失性存储单元的方法
公开(公告)号：US08409945B2
公开(公告)日：2013-04-02
申请号：US12985322
申请日：2011-01-05
申请人： Hung-Lin Shih , Tsan-Chi Chu
发明人： Hung-Lin Shih , Tsan-Chi Chu
IPC分类号： H01L21/8234 , H01L21/8247
CPC分类号： H01L29/7923 , H01L21/28282 , H01L29/66833
摘要： A method of fabricating a non-volatile memory cell is disclosed. The method includes the steps of: forming two separate charge trapping structures on a semiconductor substrate; forming first spacers on sidewalls of the two charge trapping structures; forming a gate dielectric layer on the substrate; forming a gate on the two charge trapping structures and the gate dielectric layer between the two charge trapping structures; and forming two doped regions in the substrate beside the gate.
摘要翻译：公开了一种制造非易失性存储单元的方法。该方法包括以下步骤：在半导体衬底上形成两个独立的电荷俘获结构; 在所述两个电荷俘获结构的侧壁上形成第一间隔物; 在所述基板上形成栅介电层; 在两个电荷俘获结构之间形成栅极，并在两个电荷俘获结构之间形成栅极电介质层; 以及在栅极旁边的衬底中形成两个掺杂区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式