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1. 发明申请

US20090294903A1 ANTI-FUSSE STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：抗融合结构及其制造方法
公开(公告)号：US20090294903A1
公开(公告)日：2009-12-03
申请号：US12132111
申请日：2008-06-03
申请人： Hung-Lin Shih , Wen-Shiang Liao , Tsan-Chi Chu
发明人： Hung-Lin Shih , Wen-Shiang Liao , Tsan-Chi Chu
IPC分类号： H01L23/525 , H01L21/02
CPC分类号： H01L23/5252 , H01L27/0733 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure and a method of fabricating the same are described. The anti-fuse structure is disposed over a substrate having at least one device and a copper layer therein. The anti-fuse structure includes a bottom conductive layer, an insulating layer and a top conductive layer. The bottom conductive layer is disposed over and electrically connected with the copper layer. The insulating layer is conformally disposed over the bottom conductive layer covering a corner or a downward turning portion of the bottom conductive layer to form a turning portion of the insulating layer. The top conductive layer is conformally disposed over the insulting layer covering the turning portion of the insulating layer.
摘要翻译：描述了一种抗熔丝结构及其制造方法。反熔丝结构设置在其中具有至少一个器件和铜层的衬底上。反熔丝结构包括底部导电层，绝缘层和顶部导电层。底部导电层设置在铜层上并与铜层电连接。绝缘层保形地设置在覆盖底部导电层的拐角或向下转动部分的底部导电层上，以形成绝缘层的转动部分。顶部导电层保形地设置在覆盖绝缘层的转向部分的绝缘层上。

2. 发明授权

US07423321B2 Double gate MOSFET device 有权
标题翻译：双栅MOSFET器件
公开(公告)号：US07423321B2
公开(公告)日：2008-09-09
申请号：US10976278
申请日：2004-10-29
申请人： Wen-Shiang Liao , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Wei-Tsun Shiau
IPC分类号： H01L27/01
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/4908 , H01L29/66795 , H01L29/66803
摘要： A method of fabricating a double gate MOSFET device is provided. The present invention overetches a silicon layer overlying a buried oxide layer using a hard mask of cap oxide on the silicon layer as an etching mask. As a result, source, drain and channel regions are formed extending from the buried oxide layer, and a pair of recesses are formed under the channel regions in the buried oxide layer. The channel is a fin structure with a top surface and two opposing parallelly sidewalls. The bottom recess is formed under each opposing sidewall of the fin structure. A conductive gate layer is formed straddling the fin structures. The topography of the conductive gate layer significantly deviates from the conventional plainer profile due to the bottom recess structures under the channel regions, and a more uniformly distributed doped conductive gate layer can be obtained. Hence, the depletion effect of the conductive polysilicon gate while operating the device can be suppressed and the device drive-on currents can be further enhanced.
摘要翻译：提供一种制造双栅极MOSFET器件的方法。本发明使用硅层上的氧化碳膜的硬掩模作为蚀刻掩模来蚀刻覆盖掩埋氧化物层的硅层。结果，从掩埋氧化物层形成源极，漏极和沟道区，并且在掩埋氧化物层的沟道区的下方形成一对凹部。通道是具有顶表面和两个相对的平行侧壁的翅片结构。底部凹部形成在翅片结构的每个相对侧壁下方。导电栅极层跨越翅片结构形成。导电栅极层的形貌由于在沟道区下面的底部凹陷结构而显着地偏离常规的平滑轮廓，并且可以获得更均匀分布的掺杂的导电栅极层。因此，可以抑制在操作器件时导电多晶硅栅极的耗尽效应，并且可以进一步提高器件驱动电流。

3. 发明申请

US20060172476A1 Fin field effect transistor and method for manufacturing fin field effect transistor 有权
标题翻译： Fin场效应晶体管及制造鳍式场效应晶体管的方法
公开(公告)号：US20060172476A1
公开(公告)日：2006-08-03
申请号：US11049819
申请日：2005-02-02
申请人： Wen-Shiang Liao , Wei-Tsun Shiau , Kuan-Yang Liao
发明人： Wen-Shiang Liao , Wei-Tsun Shiau , Kuan-Yang Liao
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242
CPC分类号： H01L29/66795 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66507 , H01L29/785
摘要： The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.
摘要翻译：本发明涉及一种制造包括完全硅化栅电极的鳍式场效应晶体管的方法。该方法适用于包括翅片结构，跨骑栅极，源极/漏极区域和形成在其上的电介质层的衬底，其中跨越栅极跨过鳍状结构，源极/漏极区域位于通过跨门和电介质层暴露的翅片结构覆盖基板。该方法包括以下步骤：执行平坦化处理以去除电介质层和第一自对准硅化物层的一部分，直到暴露了跨越栅极的表面，并执行自对准硅化处理以将跨门转换成完全硅化的栅电极。

4. 发明授权

US06855588B1 Method of fabricating a double gate MOSFET device 有权
标题翻译：制造双栅极MOSFET器件的方法
公开(公告)号：US06855588B1
公开(公告)日：2005-02-15
申请号：US10679381
申请日：2003-10-07
申请人： Wen-Shiang Liao , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Wei-Tsun Shiau
IPC分类号： H01L21/336 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/4908 , H01L29/66795 , H01L29/66803
摘要： A method of fabricating a double gate MOSFET device is provided. The present invention overetches a silicon layer overlying a buried oxide layer using a hard mask of cap oxide on the silicon layer as an etching mask. As a result, source, drain and channel regions are formed extending from the buried oxide layer, and a pair of recesses are formed under the channel regions in the buried oxide layer. The channel is a fin structure with a top surface and two opposing parallelly sidewalls. The bottom recess is formed under each opposing sidewall of the fin structure. A conductive gate layer is formed straddling the fin structures. The topography of the conductive gate layer significantly deviates from the conventional plainer profile due to the bottom recess structures under the channel regions, and a more uniformly distributed doped conductive gate layer can be obtained. Hence, the depletion effect of the conductive polysilicon gate while operating the device can be suppressed and the device drive-on currents can be further enhanced.
摘要翻译：提供一种制造双栅极MOSFET器件的方法。本发明使用硅层上的氧化碳膜的硬掩模作为蚀刻掩模来蚀刻覆盖掩埋氧化物层的硅层。结果，从掩埋氧化物层形成源极，漏极和沟道区，并且在掩埋氧化物层的沟道区的下方形成一对凹部。通道是具有顶表面和两个相对的平行侧壁的翅片结构。底部凹部形成在翅片结构的每个相对侧壁下方。导电栅极层跨越翅片结构形成。导电栅极层的形貌由于在沟道区下面的底部凹陷结构而显着地偏离常规的平滑轮廓，并且可以获得更均匀分布的掺杂的导电栅极层。因此，可以抑制在操作器件时导电多晶硅栅极的耗尽效应，并且可以进一步提高器件驱动电流。

5. 发明授权

US06534402B1 Method of fabricating self-aligned silicide 失效
标题翻译：制造自对准硅化物的方法
公开(公告)号：US06534402B1
公开(公告)日：2003-03-18
申请号：US10025430
申请日：2001-12-19
申请人： Wen-Shiang Liao
发明人： Wen-Shiang Liao
IPC分类号： H01L2144
CPC分类号： H01L21/28044 , H01L21/26506 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating a self-aligned silicide (salicide). A gate and a source/drain region are formed in the substrate. An ion implantation process is performed to dope surfaces of the gate and the source/drain region with metal ions. A thermal process is performed to have the metal ions react with silicon in surfaces of the gate and the source/drain region, so as to form silicide layers on the gate and the source/drain region. The metal ions include cobalt ions, titanium ions, nickel ions, platinum ions and palladium ions.
摘要翻译：制造自对准硅化物（自对准硅化物）的方法。在衬底中形成栅极和源极/漏极区域。进行离子注入工艺以用金属离子掺杂栅极和源极/漏极区域的表面。执行热处理以使金属离子与栅极和源极/漏极区域的表面中的硅反应，以在栅极和源极/漏极区域上形成硅化物层。金属离子包括钴离子，钛离子，镍离子，铂离子和钯离子。

6. 发明申请

US20070126032A1 FIN FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING FIN FIELD EFFECT TRANSISTOR 审中-公开
标题翻译： FIN场效应晶体管和制造Fin场效应晶体管的方法
公开(公告)号：US20070126032A1
公开(公告)日：2007-06-07
申请号：US11673767
申请日：2007-02-12
申请人： WEN-SHIANG LIAO , Wei-Tsun Shiau , Kuan-Yang Liao
发明人： WEN-SHIANG LIAO , Wei-Tsun Shiau , Kuan-Yang Liao
IPC分类号： H01L29/76
CPC分类号： H01L29/66795 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66507 , H01L29/785
摘要： The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.
摘要翻译：本发明涉及一种制造包括完全硅化栅电极的鳍式场效应晶体管的方法。该方法适用于包括翅片结构，跨骑栅极，源极/漏极区域和形成在其上的电介质层的衬底，其中跨越栅极跨过鳍状结构，源极/漏极区域位于通过跨门和电介质层暴露的翅片结构覆盖基板。该方法包括以下步骤：执行平坦化处理以去除电介质层和第一自对准硅化物层的一部分，直到暴露了跨越栅极的表面，并执行自对准硅化处理以将跨门转换成完全硅化的栅电极。

7. 发明授权

US06853031B2 Structure of a trapezoid-triple-gate FET 有权
标题翻译：梯形三栅极FET的结构
公开(公告)号：US06853031B2
公开(公告)日：2005-02-08
申请号：US10417167
申请日：2003-04-17
申请人： Wen-Shiang Liao , Jiunn-Ren Hwang , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Jiunn-Ren Hwang , Wei-Tsun Shiau
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66787 , H01L29/0657 , H01L29/1037 , H01L29/42376
摘要： A structure of a Trapezoid-Triple-Gate Field Effect Transistor (FET) includes a plurality of trapezoid pillars being transversely formed on an crystalline substrate or Silicon-On-Insulator (SOI) wafer. The trapezoid pillars can juxtapose with both ends connected each other. Each trapezoid pillar has a source, a channel region, and a drain aligned in longitudinal direction and a gate latitudinally superposes the channel region of the trapezoid pillar. The triple gate field effect transistor comprises a dielectric layer formed between the channel region and the conductive gate structure.
摘要翻译：梯形三栅场效应晶体管（FET）的结构包括在晶体衬底或绝缘体上硅晶片上横向形成的多个梯形柱。梯形柱可以并置，两端相互连接。每个梯形柱具有在纵向方向上排列的源极，沟道区和漏极，栅极横向叠加梯形柱的沟道区域。三栅场效应晶体管包括形成在沟道区和导电栅结构之间的电介质层。

8. 发明授权

US07732886B2 Pin photodiode structure 有权
标题翻译：引脚光电二极管结构
公开(公告)号：US07732886B2
公开(公告)日：2010-06-08
申请号：US12173807
申请日：2008-07-15
申请人： Hung-Lin Shih , Tsan-Chi Chu , Wen-Shiang Liao , Wen-Ching Tsai
发明人： Hung-Lin Shih , Tsan-Chi Chu , Wen-Shiang Liao , Wen-Ching Tsai
IPC分类号： H01L29/06
CPC分类号： H01L31/1055 , H01L27/1203 , H01L31/028 , H01L31/105 , H01L31/1808 , Y02E10/547
摘要： A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.
摘要翻译： PIN光电二极管结构包括衬底，设置在衬底中的P掺杂区域，设置在衬底中的N掺杂区域和设置在衬底中并且在P掺杂区域和N掺杂区域之间的第一半导体材料。

9. 发明授权

US07326617B2 Method of fabricating a three-dimensional multi-gate device 有权
标题翻译：制造三维多栅极器件的方法
公开(公告)号：US07326617B2
公开(公告)日：2008-02-05
申请号：US11161950
申请日：2005-08-23
申请人： Wen-Shiang Liao , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Wei-Tsun Shiau
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L29/66795 , H01L29/785
摘要： A method for fabricating a three-dimensional multi-gate device includes steps of providing a semiconductor substrate and forming a silicon fin on the semiconductor substrate, the silicon fin having a top surface and two side surfaces; forming a gate structure on the silicon fin, the gate structure partially covering the top surface and the two side surfaces of the silicon fin, and forming a spacer structure on both sides of the gate structure; forming two doped regions in the silicon fin under both sides of the gate structure; and forming a stress-adjusting layer covering the gate structure.
摘要翻译：一种制造三维多栅极器件的方法包括以下步骤：在半导体衬底上提供半导体衬底和形成硅鳍片，所述硅片具有顶表面和两个侧表面; 在所述硅片上形成栅极结构，所述栅极结构部分地覆盖所述硅片的顶表面和所述两个侧表面，并且在所述栅极结构的两侧上形成间隔结构; 在栅极结构的两侧在硅片中形成两个掺杂区域; 以及形成覆盖所述栅极结构的应力调整层。

10. 发明授权

US06740570B2 Method for forming a self-aligned silicide of a metal oxide semiconductor 有权
标题翻译：用于形成金属氧化物半导体的自对准硅化物的方法
公开(公告)号：US06740570B2
公开(公告)日：2004-05-25
申请号：US10188526
申请日：2002-07-03
申请人： Wei-Fan Chen , Wen-Shiang Liao , Ming-Lun Chang
发明人： Wei-Fan Chen , Wen-Shiang Liao , Ming-Lun Chang
IPC分类号： H01L21425
CPC分类号： H01L29/665 , H01L21/265 , H01L21/28518
摘要： The present invention discloses a method for forming a self-aligned silicidation of a metal oxide semiconductor. The feature of the present invention is to perform an ionic implanting step before carrying on the self-aligned silicidation. The implanted ion of the present invention, such as fluorine, chlorine, bromine, iodine, boron and trifluroborane, will react with the silicon on the surface of the gate structure and the silicon substrate and a barrier effect will be formed during silicidation. Therefore, a spike phenomenon because of the penetration of cobalt or the cobalt silicide into the gate structure or the source/drain regions is prevented. The junction leakage current and the breakdown voltage of the metal oxide semiconductor are avoided.
摘要翻译：本发明公开了一种形成金属氧化物半导体的自对准硅化物的方法。本发明的特征是在进行自对准硅化物之前进行离子注入步骤。本发明的注入离子如氟，氯，溴，碘，硼和三氟硼烷将与栅极结构和硅衬底的表面上的硅反应，并在硅化过程中形成屏障效应。因此，防止了钴或硅化钴渗入栅极结构或源极/漏极区域的尖峰现象。避免了金属氧化物半导体的结漏电流和击穿电压。

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